Pingcheng Dong
Orcid: 0000-0003-3975-286X
According to our database1,
Pingcheng Dong
authored at least 23 papers
between 2020 and 2025.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
CoRR, May, 2025
SR-LIO++: Efficient LiDAR-Inertial Odometry and Quantized Mapping with Sweep Reconstruction.
CoRR, March, 2025
IEEE Trans. Circuits Syst. II Express Briefs, January, 2025
A 28nm 0.22μJ/Token Memory-Compute-Intensity-Aware CNN-Transformer Accelerator with Hybrid-Attention-Based Layer-Fusion and Cascaded Pruning for Semantic-Segmentation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
Proceedings of the Thirteenth International Conference on Learning Representations, 2025
Proceedings of the Thirteenth International Conference on Learning Representations, 2025
E-NPU: A 34~126nJ/Class Event-Driven Adaptive Neural SoC with Signal-Dynamics-Aware Feature Clustering and Multi-Model In-Memory Inference/Training for Personalized Medical Wearables.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
Stereo Matching Accelerator With Re-Computation Scheme and Data-Reused Pipeline for Autonomous Vehicles.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024
Quantization Variation: A New Perspective on Training Transformers with Low-Bit Precision.
Trans. Mach. Learn. Res., 2024
Live Demonstration: A 1920×1080 129fps 4.3pJ/pixel Stereo-Matching Processor for Low-power Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Proceedings of the IEEE International Conference on Integrated Circuits, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the 2023 Conference on Empirical Methods in Natural Language Processing, 2023
2022
A Compact Hardware Architecture for Bilateral Filter With the Combination of Approximate Computing and Look-Up Table.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 4.29nJ/pixel Stereo Depth Coprocessor With Pixel Level Pipeline and Region Optimized Semi-Global Matching for IoT Application.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Post-Processing Refinement for Semi-Global Matching Algorithm Based on Real-Time FPGA.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
Real-Time FPGA-Based Binocular Stereo Vision System with Semi-Global Matching Algorithm.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021
A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020