Prakash Ramrakhyani

According to our database1, Prakash Ramrakhyani authored at least 11 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

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Bibliography

2023
SecDDR: Enabling Low-Cost Secure Memories by Protecting the DDR Interface.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Network, 2023

2021
Bandwidth Utilization Side-Channel on ML Inference Accelerators.
CoRR, 2021

BBB: Simplifying Persistent Programming using Battery-Backed Buffers.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
SESAME: Software defined Enclaves to Secure Inference Accelerators with Multi-tenant Execution.
CoRR, 2020

Shredder: Learning Noise Distributions to Protect Inference Privacy.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Shredder: Learning Noise to Protect Privacy with Partial DNN Inference on the Edge.
CoRR, 2019

Reducing Data Movement and Energy in Multilevel Cache Hierarchies without Losing Performance: Can you have it all?
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2008
Accurate system-level performance modeling and workload characterization for mobile internet devices.
Proceedings of the 9th workshop on MEmory performance, 2008

2002
A case for dynamic pipeline scaling.
Proceedings of the International Conference on Compilers, 2002


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