Gururaj Saileshwar

Orcid: 0000-0003-3542-2548

According to our database1, Gururaj Saileshwar authored at least 23 papers between 2011 and 2023.

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Bibliography

2023
The Mirage of Breaking MIRAGE: Refuting the HPCA-2023 Paper "Are Randomized Caches Truly Random?".
CoRR, 2023

The Mirage of Breaking MIRAGE: Analyzing the Modeling Pitfalls in Emerging "Attacks" on MIRAGE.
IEEE Comput. Archit. Lett., 2023

Mitigating Timing-Based NoC Side-Channel Attacks With LLC Remapping.
IEEE Comput. Archit. Lett., 2023

Practical Timing Side-Channel Attacks on Memory Compression.
Proceedings of the 44th IEEE Symposium on Security and Privacy, 2023

SQUIP: Exploiting the Scheduler Queue Contention Side Channel.
Proceedings of the 44th IEEE Symposium on Security and Privacy, 2023

Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

PT-Guard: Integrity-Protected Page Tables to Defend Against Breakthrough Rowhammer Attacks.
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Network, 2023

2022
HeapCheck: Low-cost Hardware Support for Memory Safety.
ACM Trans. Archit. Code Optim., 2022

AQUA: Scalable Rowhammer Mitigation by Quarantining Aggressor Rows at Runtime.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Hydra: enabling low-overhead mitigation of row-hammer at ultra-low thresholds via hybrid tracking.
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

On the Scalability of HeapCheck.
Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022

Randomized row-swap: mitigating Row Hammer by breaking spatial correlation between aggressor and victim rows.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021
Mentoring Opportunities in Computer Architecture: Analyzing the Past to Develop the Future.
Proceedings of the ACM/IEEE Workshop on Computer Architecture Education, 2021

MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design.
Proceedings of the 30th USENIX Security Symposium, 2021

Bespoke Cache Enclaves: Fine-Grained and Scalable Isolation from Cache Side-Channels via Flexible Set-Partitioning.
Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021

Hardware Support for Low-Cost Memory Safety.
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021

Hardware Support to Improve Fuzzing Performance and Precision.
Proceedings of the CCS '21: 2021 ACM SIGSAC Conference on Computer and Communications Security, Virtual Event, Republic of Korea, November 15, 2021

Streamline: a fast, flushless cache covert-channel attack by enabling asynchronous collusion.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2019
Lookout for Zombies: Mitigating Flush+Reload Attack on Shared Caches by Monitoring Invalidated Lines.
CoRR, 2019

CleanupSpec: An "Undo" Approach to Safe Speculation.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2011
CMOS low-noise signal conditioning with a novel differential "resistance to frequency" converter for resistive sensor applications.
Proceedings of the International SoC Design Conference, 2011


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