Wendy Elsasser

Orcid: 0009-0002-7324-0673

According to our database1, Wendy Elsasser authored at least 10 papers between 2017 and 2026.

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Timeline

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Bibliography

2026
Characterization of Coherent Data Movement in Scaled-Out Shared Memory Systems.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2026

2025
Efficient Caching with A Tag-enhanced DRAM.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2025

2024
TDRAM: Tag-enhanced DRAM for Efficient Caching.
CoRR, 2024

2023
RAMPART: RowHammer Mitigation and Repair for Server Memory Systems.
Proceedings of the International Symposium on Memory Systems, 2023

2021
Execution Dependence Extension (EDE): ISA Support for Eliminating Fences.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
The gem5 Simulator: Version 20.0+.
CoRR, 2020

2019
Reducing Data Movement and Energy in Multilevel Cache Hierarchies without Losing Performance: Can you have it all?
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
Morphable Counters: Enabling Compact Integrity Trees For Low-Overhead Secure Memories.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

SYNERGY: Rethinking Secure-Memory Design for Error-Correcting Memories.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017
Integrating DRAM power-down modes in gem5 and quantifying their impact.
Proceedings of the International Symposium on Memory Systems, 2017


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