Prasanth Viswanathan Pillai

Orcid: 0000-0002-3625-0795

Affiliations:
  • Texas Instruments (India), Bangalore, India
  • Indian Institute of Science, Bangalore, India (PhD 2020)


According to our database1, Prasanth Viswanathan Pillai authored at least 15 papers between 2008 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
Advancing Functional Safety: Improving Failure Mode Analysis and Fault Injection Using Automation and GNN Algorithms.
Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

Accelerated Design Verification Coverage Closure Using Machine Learning.
Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

Enhancing AMS Circuit Reliability: An Anomaly Dataset for Functional Safety Research in Automotive SoCs.
Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

2024
Enhancing Functional Safety in Automotive AMS Circuits through Unsupervised Machine Learning.
CoRR, 2024

Graph Learning-based Fault Criticality Analysis for Enhancing Functional Safety of E/E Systems.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2021
Exploiting Application Tolerance for Functional Safety.
Proceedings of the IEEE International Test Conference, 2021

2020
Continuous Control Set Model Predictive Control of Buck Converter.
Proceedings of the 46th Annual Conference of the IEEE Industrial Electronics Society, 2020

2019
Perturbation Based Workload Augmentation for Comprehensive Functional Safety Analysis.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2017
Safety analysis for integrated circuits in the context of hybrid systems.
Proceedings of the IEEE International Test Conference, 2017

Demystifying automotive safety and security for semiconductor developer.
Proceedings of the IEEE International Test Conference, 2017

2015
Improved Methods for Accurate Safety Analysis of Real-Life Systems.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2012
Derating based hardware optimizations in soft error tolerant designs.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

2011
Reduced overhead soft error mitigation using error control coding techniques.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

2010
Robust detection of soft errors using delayed capture methodology.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

2008
DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs.
Proceedings of the 2008 IEEE International Test Conference, 2008


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