Qirui Zhang

Orcid: 0000-0001-8113-3558

Affiliations:
  • University of Michigan, Department of electrical and computer engineering, Ann Arbor, MI, USA
  • Shanghai Jiao Tong University, School of Micro/Nano electronics, China


According to our database1, Qirui Zhang authored at least 24 papers between 2018 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
Mitigating Classical Resource Costs in Quantum Error Correction via Generalized qLDPC Predecoding.
CoRR, May, 2026

A 256-Point FFT Using Analog Floating-Point Computation With Post-Silicon Tuning.
IEEE J. Solid State Circuits, April, 2026

Pinball: A Cryogenic Predecoder for Quantum Error Correction Decoding Under Circuit-Level Noise.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2026

An 11.16μJ/token Edge SLM Decoder Accelerator with Scalable Ring-based Configuration for Token-level Pipelining in 16nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025
Pinball: A Cryogenic Predecoder for Surface Code Decoding Under Circuit-Level Noise.
CoRR, December, 2025

One-Hot Multi-Level Leaky Integrate-and-Fire Spiking Neural Networks for Enhanced Accuracy-Latency Tradeoff.
IEEE Access, 2025

A Crystal-Less Frequency-Modulation Transmitter IC with Joint Neural-Network-Driven Modulation and Coding for Low-Power Connectivity.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024
AIMMI: Audio and Image Multi-Modal Intelligence via a Low-Power SoC With 2-MByte On-Chip MRAM for IoT Devices.
IEEE J. Solid State Circuits, October, 2024

RoboVisio: A Micro-Robot Vision Domain-Specific SoC for Autonomous Navigation Enabling Fully-on-Chip Intelligence via 2-MB eMRAM.
IEEE J. Solid State Circuits, August, 2024

A 1.5-μW Fully-Integrated Keyword Spotting SoC in 28-nm CMOS With Skip-RNN and Fast-Settling Analog Frontend for Adaptive Frame Skipping.
IEEE J. Solid State Circuits, January, 2024

Quantum Circuit Simulation with Fast Tensor Decision Diagram.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023
A $1.5\mu\mathrm{W}$ End-to-End Keyword Spotting SoC with Content-Adaptive Frame Sub-Sampling and Fast-Settling Analog Frontend.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

An 8.09TOPS/W Neural Engine Leveraging Bit-Sparsified Sign-Magnitude Multiplications and Dual Adder Trees.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

TaskFusion: An Efficient Transfer Learning Architecture with Dual Delta Sparsity for Multi-Task Natural Language Processing.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

SONA: An Accelerator for Transform-Domain Neural Networks with Sparse-Orthogonal Weights.
Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

2022
Audio and Image Cross-Modal Intelligence via a 10TOPS/W 22nm SoC with Back-Propagation and Dynamic Power Gating.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 22nm 3.5TOPS/W Flexible Micro-Robotic Vision SoC with 2MB eMRAM for Fully-on-Chip Intelligence.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks.
IEEE J. Solid State Circuits, 2021

2020
A digital signal processor (DSP)-based system for embedded continuous-time cuffless blood pressure monitoring using single-channel PPG signal.
Sci. China Inf. Sci., 2020

1.03pW/b Ultra-Low Leakage Voltage-Stacked SRAM for Intelligent Edge Processors.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
Removal of Motion Artifacts in Photoplethysmograph Sensors during Intensive Exercise for Accurate Heart Rate Calculation Based on Frequency Estimation and Notch Filtering.
Sensors, 2019

2018
Motion Artifact Removal for PPG Signals based on Accurate Fundamental Frequency Estimation and Notch Filtering.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Combining Adaptive Filter and Phase Vocoder for Heart Rate Monitoring Using Photoplethysmography During Physical Exercise.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018


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