Zhehong Wang

According to our database, Zhehong Wang authored at least 14 papers between 2018 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Hardware Acceleration for Third-Generation FHE and PSI Based on It.

Zhehong Wang, Dennis Sylvester, Hun-Seok Kim, David T. Blaauw

CoRR, 2022

Audio and Image Cross-Modal Intelligence via a 10TOPS/W 22nm SoC with Back-Propagation and Dynamic Power Gating.

Zichen Fan, Hyochan An, Qirui Zhang, Boxun Xu, Li Xu, Chien-Wei Tseng, Yimai Peng, Ang Cao, Bowen Liu, Changwoo Lee, Zhehong Wang, Fanghao Liu, Guanru Wang, Shenghao Jiang, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 22nm 3.5TOPS/W Flexible Micro-Robotic Vision SoC with 2MB eMRAM for Fully-on-Chip Intelligence.

Qirui Zhang, Hyochan An, Zichen Fan, Zhehong Wang, Ziyun Li, Guanru Wang, Hun-Seok Kim, David T. Blaauw, Dennis Sylvester

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array.

Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw

IEEE J. Solid State Circuits, 2021

RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator.

Ziyun Li, Zhehong Wang, Li Xu, Qing Dong, Bowen Liu, Chin-I Su, Wen-Ting Chu, George Tsou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Dennis Sylvester, Hun-Seok Kim, David T. Blaauw

IEEE J. Solid State Circuits, 2021

2020

An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM.

Zhehong Wang, Ziyun Li, Li Xu, Qing Dong, Chin-I Su, Wen-Ting Chu, George Tsou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Dennis Sylvester, Hun-Seok Kim, David T. Blaauw

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

17.3 GCUPS Pruning-Based Pair-Hidden-Markov-Model Accelerator for Next-Generation DNA Sequencing.

Xiao Wu, Arun Subramaniyan, Zhehong Wang, Satish Narayanasamy, Reetu Das, David T. Blaauw

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

AA-ResNet: Energy Efficient All-Analog ResNet Accelerator.

Jongyup Lim, Myungjoon Choi, Bowen Liu, Taewook Kang, Ziyun Li, Zhehong Wang, Yiqun Zhang, Kaiyuan Yang, David T. Blaauw, Hun-Seok Kim, Dennis Sylvester

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array.

Zhehong Wang, Tianjun Zhang, Daichi Fujiki, Arun Subramaniyan, Xiao Wu, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, Reetuparna Das, Satish Narayanasamy, David T. Blaauw

Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019

A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination.

Qing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang, Mahmut E. Sinangil, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester

IEEE J. Solid State Circuits, 2019

Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project.

Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM.

Kaiyuan Yang, Qing Dong, Zhehong Wang, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Energy Efficient Adiabatic FRAM with 0.99 PJ/Bit Write for IoT Applications.

Supreet Jeloka, Zhehong Wang, Ruochen Xie, Sudhanshu Khanna, Steven Bartling, Dennis Sylvester, David T. Blaauw

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination.

Qing Dong, Zhehong Wang, Jongyup Lim, Yiqun Zhang, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018