Raul Chipana

According to our database, Raul Chipana authored at least 7 papers between 2010 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2014

SET Susceptibility Analysis of Clock Tree and Clock Mesh Topologies.

Raul Chipana, Fernanda Gusmão de Lima Kastensmidt

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

2012

SET susceptibility estimation of clock tree networks from layout extraction.

Raul Chipana, Fernanda Lima Kastensmidt, Jorge L. Tonfat, Ricardo Reis

Proceedings of the 13th Latin American Test Workshop, 2012

Soft-Error Probability Due to SET in Clock Tree Networks.

Raul Chipana, Eduardo Chielle, Fernanda Lima Kastensmidt, Jorge L. Tonfat, Ricardo Reis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

2011

Reliability Analysis of H-Tree Random Access Memories Implemented With Built in Current Sensors and Parity Codes for Multiple Bit Upset Correction.

Costas Argyrides, Raul Chipana, Fabian Vargas, Dhiraj K. Pradhan

IEEE Trans. Reliab., 2011

Designing and analyzing a SpaceWire router IP for soft errors detection.

Jimmy Tarrillo, Raul Chipana, Eduardo Chielle, Fernanda Lima Kastensmidt

Proceedings of the 12th Latin American Test Workshop, 2011

2010

BICS-based March test for resistive-open defect detection in SRAMs.

Raul Chipana, Letícia Maria Veiras Bolzani, Fabian Vargas

Proceedings of the 11th Latin American Test Workshop, 2010

Investigating the Use of BICS to detect resistive-open defects in SRAMs.

Raul Chipana, Letícia Maria Veiras Bolzani, Fabian Vargas, Jorge Semião, Juan J. Rodríguez-Andina, Isabel C. Teixeira, João Paulo Teixeira

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010