Eduardo Chielle

Orcid: 0000-0002-1938-912X

According to our database1, Eduardo Chielle authored at least 23 papers between 2011 and 2023.

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Bibliography

2023
CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
E3X: Encrypt-Everything-Everywhere ISA eXtensions for Private Computation.
IEEE Trans. Dependable Secur. Comput., 2022

Scalable privacy-preserving cancer type prediction with homomorphic encryption.
CoRR, 2022

Fast and Compact Interleaved Modular Multiplication Based on Carry Save Addition.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Accelerating Fully Homomorphic Encryption by Bridging Modular and Bit-Level Arithmetic.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021
Technical report: CoPHEE: Co-processor forPartially Homomorphic Encrypted Execution.
IACR Cryptol. ePrint Arch., 2021

Fast and Scalable Private Genotype Imputation Using Machine Learning and Partially Homomorphic Encryption.
IEEE Access, 2021

Real-time Private Membership Test using Homomorphic Encryption.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Practical Data-in-Use Protection Using Binary Decision Diagrams.
IEEE Access, 2020

Muon-Ra: Quantum random number generation from cosmic rays.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

2019
Experimental Applications on SRAM-Based FPGA for the NanosatC-BR2 Scientific Mission.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

CoPHEE: Co-processor for Partially Homomorphic Encrypted Execution.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

2018
E<sup>3</sup>: A Framework for Compiling C++ Programs with Encrypted Operands.
IACR Cryptol. ePrint Arch., 2018

PHYLAX: Snapshot-based profiling of real-time embedded devices via JTAG interface.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Analyzing the impact of radiation-induced failures in flash-based APSoC with and without fault tolerance techniques at CERN environment.
Microelectron. Reliab., 2017

2016
Hybrid soft error mitigation techniques for COTS processor-based systems.
Proceedings of the 17th Latin-American Test Symposium, 2016

2015
Application-Based Analysis of Register File Criticality for Reliability Assessment in Embedded Microprocessors.
J. Electron. Test., 2015

2014
Tuning software-based fault-tolerance techniques for power optimization.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Efficient metric for register file criticality in processor-based systems.
Proceedings of the 15th Latin American Test Workshop, 2014

2013
Improving error detection with selective redundancy in software-based techniques.
Proceedings of the 14th Latin American Test Workshop, 2013

2012
Configurable tool to protect processors against SEE by software-based detection techniques.
Proceedings of the 13th Latin American Test Workshop, 2012

Soft-Error Probability Due to SET in Clock Tree Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

2011
Designing and analyzing a SpaceWire router IP for soft errors detection.
Proceedings of the 12th Latin American Test Workshop, 2011


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