Jorge L. Tonfat

Orcid: 0000-0001-9346-3079

Affiliations:
  • Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil


According to our database1, Jorge L. Tonfat authored at least 15 papers between 2010 and 2019.

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Bibliography

2019
Experimental Applications on SRAM-Based FPGA for the NanosatC-BR2 Scientific Mission.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

2017
Soft error susceptibility analysis methodology of HLS designs in SRAM-based FPGAs.
Microprocess. Microsystems, 2017

Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
Leakage current analysis in static CMOS logic gates for a transistor network design approach.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Method to Analyze the Susceptibility of HLS Designs in SRAM-Based FPGAs Under Soft Errors.
Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015
Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments.
Proceedings of the 16th Latin-American Test Symposium, 2015

Energy efficient frame-level redundancy scrubbing technique for SRAM-based FPGAs.
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014
Voltage scaling and aging effects on soft error rate in SRAM-based FPGAs.
Microelectron. Reliab., 2014

Soft error rate in SRAM-based FPGAs under neutron-induced and TID effects.
Proceedings of the 15th Latin American Test Workshop, 2014

Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs.
Proceedings of the 19th IEEE European Test Symposium, 2014

2013
Using electromagnetic emanations for variability characterization in Flash-based FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2012
SET susceptibility estimation of clock tree networks from layout extraction.
Proceedings of the 13th Latin American Test Workshop, 2012

Soft-Error Probability Due to SET in Clock Tree Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

2011
Functional verification of logic modules for a Gigabit Ethernet switch.
Proceedings of the 12th Latin American Test Workshop, 2011

2010
Design and verification of a layer-2 Ethernet MAC classification engine for a Gigabit Ethernet switch.
Proceedings of the 17th IEEE International Conference on Electronics, 2010


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