Ren-Song Tsay

Orcid: 0000-0002-8997-0219

According to our database1, Ren-Song Tsay authored at least 67 papers between 1988 and 2023.

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Bibliography

2023
A Decentralized Solution for Secure Management of IoT Access Rights.
Proceedings of the Second International Conference on Innovations in Computing Research (ICR'23), 2023

Ureka: A Decentralized and Secure System for Managing Personal IoT Devices.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

A Secure and Reliable Private Key Recovery Method.
Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

2022
An Owner-managed Indirect-Permission Social Authentication Method for Private Key Recovery.
CoRR, 2022

An Embedded CNN Design for Edge Devices Based on Logarithmic Computing.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

An Adaptive High-Performance Quantization Approach for Resource-Constrained CNN Inference.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
3LSAA: A Secure And Privacy-preserving Zero-knowledge-based Data-sharing Approach Under An Untrusted Environment.
CoRR, 2021

A Double-Linked Blockchain Approach Based on Proof-of-Refundable-Tax Consensus Algorithm.
CoRR, 2021

A Precise Program Phase Identification Method Based on Frequency Domain Analysis.
CoRR, 2021

An Effective Early Multi-core System Shared Cache Design Method Based on Reuse-distance Analysis.
CoRR, 2021

A Fast-and-Effective Early-Stage Multi-level Cache Optimization Method Based on Reuse-Distance Analysis.
CoRR, 2021

Analytical Process Scheduling Optimization for Heterogeneous Multi-core Systems.
CoRR, 2021

An Effective Parallel Program Debugging Approach Based on Timing Annotation.
CoRR, 2021

A High-Performance Adaptive Quantization Approach for Edge CNN Applications.
CoRR, 2021

2020
A Virtualization-Assisted Full-System Simulation Approach for the Verification of System Intercomponent Interactions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Very Compact Embedded CNN Processor Design Based on Logarithmic Computing.
CoRR, 2020

CORONA: A k-COnnected RObust Interconnection Network Generation Algorithm.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

VIRA: a virtualization assisted deterministic system-level simulations.
Proceedings of the SAC '20: The 35th ACM/SIGAPP Symposium on Applied Computing, online event, [Brno, Czech Republic], March 30, 2020

A Heuristic Region-based Concurrency Bug Testing Approach.
Proceedings of the IEEE International Conference on Parallel & Distributed Processing with Applications, 2020

An Optimal Slack-Based Course Scheduling Algorithm for Personalised Study Plans.
Proceedings of the ICEIT 2020, 2020

Designing A Compact Convolutional Neural Network Processor on Embedded FPGAs.
Proceedings of the IEEE Global Conference on Artificial Intelligence and Internet of Things, 2020

A Pipeline-Based Scheduler for Optimizing Latency of Convolution Neural Network Inference over Heterogeneous Multicore Systems.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2018
A highly efficient full-system virtual prototype based on virtualization-assisted approach.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2016
An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices.
Proceedings of the 2016 IEEE International Conference on Healthcare Informatics, 2016

Poster Paper: An Accurate Crowdsourcing-Based Adaptive Fall Detection Approach Using Smart Devices.
Proceedings of the 2016 IEEE International Conference on Healthcare Informatics, 2016

An accurate and flexible early memory system power evaluation approach using a microcomponent method.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015
Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

AROMA: A highly accurate microcomponent-based approach for embedded processor power analysis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Automatic timing-coherent transactor generation for mixed-level simulations.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
An activity-sensitive contention delay model for highly efficient deterministic full-system simulations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
A distributed timing synchronization technique for parallel multi-core instruction-set simulation.
ACM Trans. Embed. Comput. Syst., 2013

Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus.
ACM Trans. Embed. Comput. Syst., 2013

MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A basic-block power annotation approach for fast and accurate embedded software power estimation.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A fast and accurate instruction-oriented processor simulation approach.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A Cycle Count Accurate TLM bus modeling approach.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations.
Proceedings of the Design, Automation and Test in Europe, 2013

An efficient hybrid synchronization technique for scalable multi-core instruction set simulations.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
An Extended SystemC Framework for Efficient HW/SW Co-Simulation.
ACM Trans. Design Autom. Electr. Syst., 2012

A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Real-Time Tone-Mapping Processor with Integrated Photographic and Gradient Compression using 0.13 μm Technology on an Arm Soc Platform.
J. Signal Process. Syst., 2011

From academic ideas to practical physical design tools.
Proceedings of the 2011 International Symposium on Physical Design, 2011

DOM: A Data-dependency-Oriented Modeling approach for efficient simulation of OS preemptive scheduling.
Proceedings of the Design, Automation and Test in Europe, 2011

Cycle-count-accurate processor modeling for fast and accurate system-level simulation.
Proceedings of the Design, Automation and Test in Europe, 2011

A shared-variable-based synchronization approach to efficient cache coherence simulation for multi-core systems.
Proceedings of the Design, Automation and Test in Europe, 2011

A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation.
Proceedings of the 48th Design Automation Conference, 2011

Cut-demand based routing resource allocation and consolidation for routability enhancement.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation.
Proceedings of the Design, Automation and Test in Europe, 2010

Source-level timing annotation for fast and accurate TLM computation model generation.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
How to consider shorts and guarantee yield rate improvement for redundant wire insertion.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

An effective synchronization approach for fast and accurate multi-core instruction-set simulation.
Proceedings of the 9th ACM & IEEE International conference on Embedded software, 2009

Cycle count accurate memory modeling in system level design.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video.
Proceedings of the International Conference on Image Processing, 2008

2007
An Entrepreneurship Emulation Platform.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

1993
An exact zero-skew clock routing algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992
Clock tree regeneration.
Proceedings of the Second Great Lakes Symposium on VLSI, 1992

Performance-Driven System Partitioning on Multi-Chip Modules.
Proceedings of the 29th Design Automation Conference, 1992

1991
A new method for floor planning using topological constraint reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Exact Zero Skew.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

An Analytic Net Weighting Approach for Performance Optimization in Circuit Placement.
Proceedings of the 28th Design Automation Conference, 1991

1990
Floorplanning by Topological Constraint Reduction.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
A new approach to sea-of-gates global routing.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
PROUD: a sea-of-gates placement algorithm.
IEEE Des. Test, 1988

Proud: A Fast Sea-of-Gates Placement Algorithm.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988


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