Wai-Kei Mak

According to our database1, Wai-Kei Mak authored at least 68 papers between 1990 and 2018.

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Bibliography

2018
Pin Assignment Optimization for Multi-2.5D FPGA-based Systems.
Proceedings of the 2018 International Symposium on Physical Design, 2018

A practical detailed placement algorithm under multi-cell spacing constraints.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Minimum Implant Area-Aware Placement and Threshold Voltage Refinement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

A routing framework for technology migration with bump encroachment.
Integration, 2017

Pin Accessibility-Driven Detailed Placement Refinement.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Making split fabrication synergistically secure and manufacturable.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Making split fabrication synergistically secure and manufacturable.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Mixed-Cell-Height Standard Cell Placement Legalization.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Optimizing DSA-MP decomposition and redundant via insertion with dummy vias.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Minimum implant area-aware placement and threshold voltage refinement.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A fast parallel approach for common path pessimism removal.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
E-Beam Lithography Character and Stencil Co-Optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Double patterning-aware detailed routing with mask usage balancing.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Flexible packed stencil design with multiple shaping apertures for e-beam lithography.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement.
IEEE Trans. VLSI Syst., 2013

Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Rethinking the Wirelength Benefit of 3-D Integration.
IEEE Trans. VLSI Syst., 2012

ISPD11: Power-Driven Flip-Flop Merging and Relocation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Pad Assignment for Die-Stacking System-in-Package Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

2011
SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Power-driven flip-flop merging and relocation.
Proceedings of the 2011 International Symposium on Physical Design, 2011

Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Cut-demand based routing resource allocation and consolidation for routability enhancement.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
SafeChoice: a novel clustering algorithm for wirelength-driven placement.
Proceedings of the 2010 International Symposium on Physical Design, 2010

FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009
Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Pad assignment for die-stacking System-in-Package design.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

How to consider shorts and guarantee yield rate improvement for redundant wire insertion.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Signal skew aware floorplanning and bumper signal assignment technique for flip-chip.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Guest Editorial: Field Programmable Technology.
Signal Processing Systems, 2008

Low-power gated and buffered clock network construction.
ACM Trans. Design Autom. Electr. Syst., 2008

2007
Optimal Buffering of FPGA Interconnect for Expected Delay Optimization.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Voltage Island Generation under Performance Requirement for SoC Designs.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Modern FPGA constrained placement.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Power minimization algorithms for LUT-based FPGA technology mapping.
ACM Trans. Design Autom. Electr. Syst., 2004

Force-Directed Performance-Driven Placement Algorithm for FPGAs.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

2003
Clustering based acyclic multi-way partitioning.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

I/O placement for FPGAs with multiple I/O standards.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Efficient LUT-based FPGA technology mapping for power minimization.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Temporal logic replication for dynamically reconfigurable FPGA partitioning.
Proceedings of 2002 International Symposium on Physical Design, 2002

2001
Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Faster and more accurate wiring evaluation in interconnect-centric floorplanning.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000
A fast hypergraph min-cut algorithm for circuit partitioning.
Integration, 2000

1999
Monte Carlo bounding techniques for determining solution quality in stochastic programs.
Oper. Res. Lett., 1999

A fast hypergraph minimum cut algorithm.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Performance-driven board-level routing for FPGA-based logic emulation.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract).
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997
Board-level multiterminal net routing for FPGA-based logic emulation.
ACM Trans. Design Autom. Electr. Syst., 1997

Channel Segmentation Design for Symmentrical FPGAs.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
Minimum replication min-cut partitioning.
ICCAD, 1996

1995
Board-level multi-terminal net routing for FPGA-based logic emulation.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

On Optimal Board-Level Routing for FPGA-Based Logic Emulation.
Proceedings of the 32st Conference on Design Automation, 1995

1993
Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993

1990
Implementation of the Ficus Replicated File System.
Proceedings of the Usenix Summer 1990 Technical Conference, 1990


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