Wai-Kei Mak

Proceedings of the 2024 International Symposium on Physical Design, 2024

2023

Drain-to-Drain Abutment-Aware Detailed Placement Refinement for Power Staple Insertion Optimization.

[BibT_eX]

[DOI]

Yu-Jin Xie

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023

Hybrid-Row-Height Design Placement Legalization Considering Cell Variants.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement.

[BibT_eX]

[DOI]

Chung-Hsien Wu

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Reinforcement Learning and DEAR Framework for Solving the Qubit Mapping Problem.

[BibT_eX]

[DOI]

Ching-Yao Huang

Chi-Hsiang Lien

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

HybridGP: Global Placement for Hybrid-Row-Height Designs.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems With Time-Multiplexed I/Os.

[BibT_eX]

[DOI]

Yu-Chen Liao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs.

[BibT_eX]

[DOI]

Proceedings of the ISPD '21: International Symposium on Physical Design, 2021

A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits.

[BibT_eX]

[DOI]

Ching-Cheng Wang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Manufacturing-Aware Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement Refinement.

[BibT_eX]

[DOI]

Yu-Jin Xie

Kuan-Yu Chen

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2018

Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Pin Assignment Optimization for Multi-2.5D FPGA-based Systems.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on Physical Design, 2018

A practical detailed placement algorithm under multi-cell spacing constraints.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

2017

Minimum Implant Area-Aware Placement and Threshold Voltage Refinement.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

A routing framework for technology migration with bump encroachment.

[BibT_eX]

[DOI]

Integr., 2017

Pin Accessibility-Driven Detailed Placement Refinement.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Making split fabrication synergistically secure and manufacturable.

[BibT_eX]

[DOI]

Jeyavijayan Rajendran

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Mixed-Cell-Height Standard Cell Placement Legalization.

[BibT_eX]

[DOI]

Chung-Yao Hung

Peng-Yi Chou

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Optimizing DSA-MP decomposition and redundant via insertion with dummy vias.

[BibT_eX]

[DOI]

Chung-Yao Hung

Peng-Yi Chou

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Minimum implant area-aware placement and threshold voltage refinement.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography.

[BibT_eX]

[DOI]

Chris C. N. Chu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography.

[BibT_eX]

[DOI]

Chris C. N. Chu

Proceedings of the 52nd Annual Design Automation Conference, 2015

A fast parallel approach for common path pessimism removal.

[BibT_eX]

[DOI]

Chung-Hao Tsai

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

E-Beam Lithography Character and Stencil Co-Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Double patterning-aware detailed routing with mask usage balancing.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules.

[BibT_eX]

[DOI]

Sheng-Kai Wu

Po-Yi Hsu

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Flexible packed stencil design with multiple shaping apertures for e-beam lithography.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement.

[BibT_eX]

[DOI]

Cha-Ru Li

Ting-Chi Wang

IEEE Trans. Very Large Scale Integr. Syst., 2013

Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Rethinking the Wirelength Benefit of 3-D Integration.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

ISPD11: Power-Driven Flip-Flop Merging and Relocation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Pad Assignment for Die-Stacking System-in-Package Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011

SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement.

[BibT_eX]

[DOI]

Jackey Z. Yan

Chris C. N. Chu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction.

[BibT_eX]

[DOI]

Gaurav Ajwani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Power-driven flip-flop merging and relocation.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on Physical Design, 2011

Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Cut-demand based routing resource allocation and consolidation for routability enhancement.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

SafeChoice: a novel clustering algorithm for wirelength-driven placement.

[BibT_eX]

[DOI]

Jackey Z. Yan

Proceedings of the 2010 International Symposium on Physical Design, 2010

Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design.

[BibT_eX]

[DOI]

De-Yu Liu

Ting-Chi Wang

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution.

[BibT_eX]

[DOI]

Chun-Yu Chuang

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

How to consider shorts and guarantee yield rate improvement for redundant wire insertion.

[BibT_eX]

[DOI]

Fong-Yuan Chang

Ren-Song Tsay

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Signal skew aware floorplanning and bumper signal assignment technique for flip-chip.

[BibT_eX]

[DOI]

Cheng-Yu Wang

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Guest Editorial: Field Programmable Technology.

[BibT_eX]

[DOI]

George A. Constantinides

Theerayod Wiangtong

J. Signal Process. Syst., 2008

Low-power gated and buffered clock network construction.

[BibT_eX]

[DOI]

Wei-Chung Chao

ACM Trans. Design Autom. Electr. Syst., 2008

2007

Optimal Buffering of FPGA Interconnect for Expected Delay Optimization.

[BibT_eX]

[DOI]

Yi-Ru He

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Voltage Island Generation under Performance Requirement for SoC Designs.

[BibT_eX]

[DOI]

Jr-Wei Chen

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers.

[BibT_eX]

[DOI]

Chien-Chang Chen

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Modern FPGA constrained placement.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Power minimization algorithms for LUT-based FPGA technology mapping.

[BibT_eX]

[DOI]

Hao Li

Srinivas Katkoori

ACM Trans. Design Autom. Electr. Syst., 2004

I/O placement for FPGAs with multiple I/O standards.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Force-Directed Performance-Driven Placement Algorithm for FPGAs.

[BibT_eX]

[DOI]

Hao Li

Srinivas Katkoori

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

2003

Temporal logic replication for dynamically reconfigurable FPGA partitioning.

[BibT_eX]

[DOI]

Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Clustering based acyclic multi-way partitioning.

[BibT_eX]

[DOI]

Eric S. H. Wong

Evangeline F. Y. Young

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Efficient LUT-based FPGA technology mapping for power minimization.

[BibT_eX]

[DOI]

Hao Li

Srinivas Katkoori

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001

Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Physical Design, 2001

Faster and more accurate wiring evaluation in interconnect-centric floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000

A fast hypergraph min-cut algorithm for circuit partitioning.

[BibT_eX]

[DOI]

Integr., 2000

1999

Monte Carlo bounding techniques for determining solution quality in stochastic programs.

[BibT_eX]

[DOI]

David P. Morton

R. Kevin Wood

Oper. Res. Lett., 1999

A fast hypergraph minimum cut algorithm.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998

Performance-driven board-level routing for FPGA-based logic emulation.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract).

[BibT_eX]

[DOI]

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

1997

Board-level multiterminal net routing for FPGA-based logic emulation.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1997

Minimum replication min-cut partitioning.

[BibT_eX]

[DOI]

Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

On optimal board-level routing for FPGA-based logic emulation.

[BibT_eX]

[DOI]

Martin D. F. Wong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Channel Segmentation Design for Symmentrical FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1995

Board-level multi-terminal net routing for FPGA-based logic emulation.

[BibT_eX]

[DOI]