Renato Fernandes Hentschke

According to our database1, Renato Fernandes Hentschke authored at least 23 papers between 2002 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Declarative Language for Geometric Pattern Matching in VLSI Process Rule Modeling.
Proceedings of the 2019 International Symposium on Physical Design, 2019

2014
Algorithms for Maze Routing With Exact Matching Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2012
Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias.
RITA, 2012

Maze routing algorithms with exact matching constraints for analog and mixed signal designs.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011
An Algorithmic Study of Exact Route Matching for Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

2009
Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Exact route matching algorithms for analog and mixed signal integrated circuits.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2007
Cell placement on graphics processing units.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

3D-Vias Aware Quadratic Placement for 3D VLSI Circuits.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Maze routing steiner trees with effective critical sink optimization.
Proceedings of the 2007 International Symposium on Physical Design, 2007

A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire Length.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A Method for I/O Pins Partitioning Targeting 3D VLSI Circuits.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
Improving run times by pruned application of synthesis transforms.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Blue Macaw: A Didactic Placement Tool Using Simulated Annealing.
Proceedings of the New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design, 2005

2004
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs.
IEEE Des. Test Comput., 2004

Design Space Exploration with Automatic Generation of IP-Based Embedded Software.
Proceedings of the Design Methods and Applications for Distributed Embedded Systems, 2004

2003
A study on the performance of fast initial placement algorithms.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Plic-Plac: a novel constructive algorithm for placement.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002


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