Ricardo Fernández Pascual

Orcid: 0000-0002-2337-4369

According to our database1, Ricardo Fernández Pascual authored at least 36 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
On the interactions between ILP and TLP with hardware transactional memory.
Microprocess. Microsystems, 2024

2022
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory.
IEEE Trans. Parallel Distributed Syst., 2022

Analysing software prefetching opportunities in hardware transactional memory.
J. Supercomput., 2022

Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory.
Proceedings of the 30th Euromicro International Conference on Parallel, 2022

2020
Concurrent Irrevocability in Best-Effort Hardware Transactional Memory.
IEEE Trans. Parallel Distributed Syst., 2020

PfTouch: Concurrent page-fault handling for Intel restricted transactional memory.
J. Parallel Distributed Comput., 2020

2019
Way Combination for an Adaptive and Scalable Coherence Directory.
IEEE Trans. Parallel Distributed Syst., 2019

2017
To be silent or not: on the impact of evictions of clean data in cache-coherent multicores.
J. Supercomput., 2017

A dedicated private-shared cache design for scalable multiprocessors.
Concurr. Comput. Pract. Exp., 2017

Way-combining directory: an adaptive and scalable low-cost coherence directory.
Proceedings of the International Conference on Supercomputing, 2017

2016
Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study.
J. Supercomput., 2016

New compactly supported spatiotemporal covariance functions from SPDEs.
Stat. Methods Appl., 2016

Plug-in prediction intervals for a special class of standard ARH(1) processes.
J. Multivar. Anal., 2016

Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015
ICCI: In-Cache Coherence Information.
IEEE Trans. Computers, 2015

Early Experiences with Separate Caches for Private and Shared Data.
Proceedings of the 11th IEEE International Conference on e-Science, 2015

2014
Managing resources dynamically in hybrid photonic-electronic networks-on-chip.
Concurr. Comput. Pract. Exp., 2014

Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs.
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014

2012
Extending Magny-Cours Cache Coherence.
IEEE Trans. Computers, 2012

DAPSCO: Distance-aware partially shared cache organization.
ACM Trans. Archit. Code Optim., 2012

Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

The Spanish Parallel Programming Contests and its Use as an Educational Resource.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

An Experience of Early Initiation to Parallelism in the Computing Engineering Degree at the University of Murcia, Spain.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011
Energy-Efficient Cache Coherence Protocols in Chip-Multiprocessors for Server Consolidation.
Proceedings of the International Conference on Parallel Processing, 2011

2010
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level.
IEEE Trans. Parallel Distributed Syst., 2010

Analyzing Cache Coherence Protocols for Server Consolidation.
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010

EMC<sup>2</sup>: Extending Magny-Cours coherence for large-scale servers.
Proceedings of the 2010 International Conference on High Performance Computing, 2010

2008
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures.
IEEE Trans. Parallel Distributed Syst., 2008

Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors.
J. Parallel Distributed Comput., 2008

An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs.
Proceedings of the High Performance Computing, 2008

A fault-tolerant directory-based cache coherence protocol for CMP architectures.
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

2007
An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology.
Parallel Comput., 2007

A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures.
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007

2005
Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures.
Proceedings of the 13th Euromicro Workshop on Parallel, 2005

2003
Multiscale estimation of processes related to the fractional Black-Scholes equation.
Comput. Stat., 2003


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