Robert D. Mullins

Orcid: 0000-0002-8393-2748

  • University of Cambridge, UK

According to our database1, Robert D. Mullins authored at least 64 papers between 1995 and 2024.

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PhD thesis 


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Beyond Slow Signs in High-fidelity Model Extraction.
CoRR, 2024

Locking Machine Learning Models into Hardware.
CoRR, 2024

Architectural Neural Backdoors from First Principles.
CoRR, 2024

ImpNet: Imperceptible and blackbox-undetectable backdoors in compiled neural networks.
Proceedings of the IEEE Conference on Secure and Trustworthy Machine Learning, 2024

LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation.
CoRR, 2023

Human-Producible Adversarial Examples.
CoRR, 2023

Dynamic Stashing Quantization for Efficient Transformer Training.
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2023, 2023

Architectural Backdoors in Neural Networks.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

Revisiting Structured Dropout.
Proceedings of the Asian Conference on Machine Learning, 2023

Revisiting Automated Prompting: Are We Actually Doing Better?
Proceedings of the 61st Annual Meeting of the Association for Computational Linguistics (Volume 2: Short Papers), 2023

Sim-D: A SIMD Accelerator for Hard Real-Time Systems.
IEEE Trans. Computers, 2022

DARTFormer: Finding The Best Type Of Attention.
CoRR, 2022

Wide Attention Is The Way Forward For Transformers.
CoRR, 2022

ImpNet: Imperceptible and blackbox-undetectable backdoors in compiled neural networks.
CoRR, 2022

Augmentation Backdoors.
CoRR, 2022

Revisiting Embeddings for Graph Neural Networks.
CoRR, 2022

Efficient Adversarial Training With Data Pruning.
CoRR, 2022

Muntjac - Open Source Multicore RV64 Linux-capable SoC.
CoRR, 2022

Model Architecture Adaption for Bayesian Neural Networks.
CoRR, 2022

Rapid Model Architecture Adaption for Meta-Learning.
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

Trace-and-brace (TAB): bespoke software countermeasures against soft errors.
Proceedings of the LCTES '22: 23rd ACM SIGPLAN/SIGBED International Conference on Languages, 2022

DAdaQuant: Doubly-adaptive quantization for communication-efficient Federated Learning.
Proceedings of the International Conference on Machine Learning, 2022

Lane Compression: A Lightweight Lossless Compression Method for Machine Learning on Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2021

Sponge Examples: Energy-Latency Attacks on Neural Networks.
Proceedings of the IEEE European Symposium on Security and Privacy, 2021

Performance analysis of single board computer clusters.
Future Gener. Comput. Syst., 2020

Nudge Attacks on Point-Cloud DNNs.
CoRR, 2020

Learned Low Precision Graph Neural Networks.
CoRR, 2020

Accelerate Cycle-Level Full-System Simulation of Multi-Core RISC-V Systems with Binary Translation.
CoRR, 2020

Probabilistic Dual Network Architecture Search on Graphs.
CoRR, 2020

Blackbox Attacks on Reinforcement Learning Agents Using Approximated Temporal Information.
Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2020

Towards Certifiable Adversarial Sample Detection.
Proceedings of the AISec@CCS 2020: Proceedings of the 13th ACM Workshop on Artificial Intelligence and Security, 2020

Fast TLB Simulation for RISC-V Systems.
CoRR, 2019

Efficient and Effective Quantization for Sparse DNNs.
CoRR, 2019

Sitatapatra: Blocking the Transfer of Adversarial Samples.
CoRR, 2019

Focused Quantization for Sparse CNNs.
Proceedings of the Advances in Neural Information Processing Systems 32: Annual Conference on Neural Information Processing Systems 2019, 2019

To Compress Or Not To Compress: Understanding The Interactions Between Adversarial Attacks And Neural Network Compression.
Proceedings of the Second Conference on Machine Learning and Systems, SysML 2019, 2019

Characterizing Sources of Ineffectual Computations in Deep Learning Networks.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Dynamic Channel Pruning: Feature Boosting and Suppression.
Proceedings of the 7th International Conference on Learning Representations, 2019

Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs.
Proceedings of the International Conference on Field-Programmable Technology, 2019

Efficient Winograd or Cook-Toom Convolution Kernel Implementation on Widely Used Mobile CPUs.
Proceedings of the 2nd Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications, 2019

Commodity single board computer clusters and their applications.
Future Gener. Comput. Syst., 2018

On the Reduction of Computational Complexity of Deep Convolutional Neural Networks.
Entropy, 2018

The Taboo Trap: Behavioural Detection of Adversarial Samples.
CoRR, 2018

Next generation single board clusters.
Proceedings of the 2018 IEEE/IFIP Network Operations and Management Symposium, 2018

Mayo: A Framework for Auto-generating Hardware Friendly Deep Neural Networks.
Proceedings of the 2nd International Workshop on Embedded and Mobile Deep Learning, 2018

ADaPT: optimizing CNN inference on IoT and mobile devices using approximately separable 1-D kernels.
Proceedings of the 1st International Conference on Internet of Things and Machine Learning, 2017

1D-FALCON: Accelerating Deep Convolutional Neural Network Inference by Co-optimization of Models and Underlying Arithmetic Implementation.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2017, 2017

Configurable memory systems for embedded many-core processors.
CoRR, 2016

Performance implications of transient loop-carried data dependences in automatically parallelized loops.
Proceedings of the 25th International Conference on Compiler Construction, 2016

Exploiting Tightly-Coupled Cores.
J. Signal Process. Syst., 2015

Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocessors.
IEEE Trans. Computers, 2013

An Energy and Performance Exploration of Network-on-Chip Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2009

A Network of Time-Division Multiplexed Wiring for FPGAs.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

A Power and Energy Exploration of Network-on-Chip Architectures.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Demystifying Data-Driven and Pausible Clocking Schemes.
Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007), 2007

The design and implementation of a low-latency on-chip network.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Low-Latency Virtual-Channel Routers for On-Chip Networks.
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

Balanced self-checking asynchronous logic for smart card applications.
Microprocess. Microsystems, 2003

Security Evaluation of Asynchronous Circuits.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2003

Point to Point GALS Interconnect.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

Improving Smart Card Security Using Self-Timed Circuits.
Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

A Fully Asynchronous Superscalar Architecture.
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999

Micronets: a model for decentralising control in asynchronous processor architectures.
Proceedings of the Second Working Conference on Asynchronous Design Methodologies, 1995