Simone Campanoni

Orcid: 0000-0001-9806-7016

According to our database1, Simone Campanoni authored at least 55 papers between 2008 and 2024.

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Bibliography

2024
The Parallel Semantics Program Dependence Graph.
CoRR, 2024

Representing Data Collections in an SSA Form.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2024

Getting a Handle on Unmanaged Memory.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

TrackFM: Far-out Compiler Support for a Far Memory World.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

Compiling Loop-Based Nested Parallelism for Irregular Workloads.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
ExGen: Cross-platform, Automated Exploit Generation for Smart Contract Vulnerabilities.
IEEE Trans. Dependable Secur. Comput., 2023

PROMPT: A Fast and Extensible Memory Profiling Framework.
CoRR, 2023

Guess & Sketch: Language Model Guided Transpilation.
CoRR, 2023

EMISSARY: Enhanced Miss Awareness Replacement Policy for L2 Instruction Caching.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

WARDen: Specializing Cache Coherence for High-Level Parallel Languages.
Proceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization, 2023

Program State Element Characterization.
Proceedings of the 21st ACM/IEEE International Symposium on Code Generation and Optimization, 2023

SPLENDID: Supporting Parallel LLVM-IR Enhanced Natural Decompilation for Interactive Development.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
WARio: efficient code generation for intermittent computing.
Proceedings of the PLDI '22: 43rd ACM SIGPLAN International Conference on Programming Language Design and Implementation, San Diego, CA, USA, June 13, 2022

NOELLE Offers Empowering LLVM Extensions.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2022

CARAT CAKE: replacing paging via compiler/kernel cooperation.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2021
NOELLE Offers Empowering LLVM Extensions.
CoRR, 2021

Paths to OpenMP in the kernel.
Proceedings of the International Conference for High Performance Computing, 2021

The Case for an Interwoven Parallel Hardware/Software Stack.
Proceedings of the 2021 SC Workshops Supplementary Proceedings, 2021

Task parallel assembly language for uncompromising parallelism.
Proceedings of the PLDI '21: 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2021

CODE: Compiler-based Neuron-aware Ensemble training.
Proceedings of Machine Learning and Systems 2021, 2021

Quantifying the Semantic Gap Between Serial and Parallel Programming.
Proceedings of the IEEE International Symposium on Workload Characterization, 2021

2020
Compiler-based timing for extremely fine-grain preemptive parallelism.
Proceedings of the International Conference for High Performance Computing, 2020

CARAT: a case for virtual memory through compiler- and runtime-based address translation.
Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2020

SCAF: a speculation-aware collaborative dependence analysis framework.
Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2020

Introducing the pseudorandom value generator selection in the compilation toolchain.
Proceedings of the CGO '20: 18th ACM/IEEE International Symposium on Code Generation and Optimization, 2020

Perspective: A Sensible Approach to Speculative Automatic Parallelization.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Workload Characterization of Nondeterministic Programs Parallelized by STATS.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Time squeezing for tiny devices.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018
Temporal Approximate Function Memoization.
IEEE Micro, 2018

Compiler-guided instruction-level clock scheduling for timing speculative processors.
Proceedings of the 55th Annual Design Automation Conference, 2018

Unconventional Parallelization of Nondeterministic Applications.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Automatically accelerating non-numerical programs by architecture-compiler co-design.
Commun. ACM, 2017

POSTER: The Liberation Day of Nondeterministic Programs.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Performance implications of transient loop-carried data dependences in automatically parallelized loops.
Proceedings of the 25th International Conference on Compiler Construction, 2016

2015
Power-awareness and smart-resource management in embedded computing systems.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

HELIX-UP: relaxing program semantics to unleash parallelization.
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015

2014
HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2012
Optimal Design of Wireless Sensor Networks.
Proceedings of the Methodologies and Technologies for Networked Enterprises, 2012

Helix: Making the Extraction of Thread-Level Parallelism Mainstream.
IEEE Micro, 2012

Metronome: operating system level performance management via self-adaptive computing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

The HELIX project: overview and directions.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

HELIX: automatic parallelization of irregular programs for chip multiprocessing.
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012

2011
Guide to ILDJIT.
Springer Briefs in Computer Science, Springer, ISBN: 978-1-4471-2194-7, 2011

Voltage Noise in Production Processors.
IEEE Micro, 2011

Static memory management within bytecode languages on multicore systems.
Proceedings of the 1st International Workshop on Computing in Heterogeneous, 2011

2010
Eliminating voltage emergencies via software-guided code transformations.
ACM Trans. Archit. Code Optim., 2010

A highly flexible, parallel virtual machine: design and experience of ILDJIT.
Softw. Pract. Exp., 2010

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Parallelism and Retargetability in the ILDJIT Dynamic Compiler.
Proceedings of the ARCS '10, 2010

2009
Just-In-Time compilation on ARM processors.
Proceedings of the 4th workshop on the Implementation, 2009

Traces of Control-Flow Graphs.
Proceedings of the Developments in Language Theory, 13th International Conference, 2009

Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack.
Proceedings of the 46th Design Automation Conference, 2009

Dynamic Look Ahead Compilation: A Technique to Hide JIT Compilation Latencies in Multicore Environment.
Proceedings of the Compiler Construction, 18th International Conference, 2009

2008
A parallel dynamic compiler for CIL bytecode.
ACM SIGPLAN Notices, 2008

Models and Tradeoffs in WSN System-Level Design.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008


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