Simone Campanoni

According to our database1, Simone Campanoni
  • authored at least 26 papers between 2008 and 2018.
  • has a "Dijkstra number"2 of five.



In proceedings 
PhD thesis 




Compiler-guided instruction-level clock scheduling for timing speculative processors.
Proceedings of the 55th Annual Design Automation Conference, 2018

Unconventional Parallelization of Nondeterministic Applications.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

Automatically accelerating non-numerical programs by architecture-compiler co-design.
Commun. ACM, 2017

POSTER: The Liberation Day of Nondeterministic Programs.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

Performance implications of transient loop-carried data dependences in automatically parallelized loops.
Proceedings of the 25th International Conference on Compiler Construction, 2016

Power-awareness and smart-resource management in embedded computing systems.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

HELIX-UP: relaxing program semantics to unleash parallelization.
Proceedings of the 13th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2015

HELIX-RC: An architecture-compiler co-design for automatic parallelization of irregular programs.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Optimal Design of Wireless Sensor Networks.
Proceedings of the Methodologies and Technologies for Networked Enterprises, 2012

Helix: Making the Extraction of Thread-Level Parallelism Mainstream.
IEEE Micro, 2012

Metronome: operating system level performance management via self-adaptive computing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

The HELIX project: overview and directions.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

HELIX: automatic parallelization of irregular programs for chip multiprocessing.
Proceedings of the 10th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2012

Guide to ILDJIT.
Springer Briefs in Computer Science, Springer, ISBN: 978-1-4471-2194-7, 2011

Voltage Noise in Production Processors.
IEEE Micro, 2011

Static memory management within bytecode languages on multicore systems.
Proceedings of the 1st International Workshop on Computing in Heterogeneous, 2011

Eliminating voltage emergencies via software-guided code transformations.
TACO, 2010

A highly flexible, parallel virtual machine: design and experience of ILDJIT.
Softw., Pract. Exper., 2010

Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Parallelism and Retargetability in the ILDJIT Dynamic Compiler.
Proceedings of the ARCS '10, 2010

Just-In-Time compilation on ARM processors.
Proceedings of the 4th workshop on the Implementation, 2009

Traces of Control-Flow Graphs.
Proceedings of the Developments in Language Theory, 13th International Conference, 2009

Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack.
Proceedings of the 46th Design Automation Conference, 2009

Dynamic Look Ahead Compilation: A Technique to Hide JIT Compilation Latencies in Multicore Environment.
Proceedings of the Compiler Construction, 18th International Conference, 2009

A parallel dynamic compiler for CIL bytecode.
SIGPLAN Notices, 2008

Models and Tradeoffs in WSN System-Level Design.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008