Timon Evenblij

Orcid: 0000-0002-5337-0617

According to our database1, Timon Evenblij authored at least 14 papers between 2019 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Calibrating DRAMPower Model for HPC: A Runtime Perspective From Real-Time Measurements.
IEEE Comput. Archit. Lett., 2026

Characterizing Machine Learning Force Fields as Emerging Molecular Dynamics Workloads on Graphics Processing Units.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2026

2025
System-performance and cost modeling of Large Language Model training and inference.
CoRR, July, 2025

PARL: Page Allocation in hybrid main memory using Reinforcement Learning.
J. Syst. Archit., 2025

Energon: A Sustainability-Driven Modeling Framework for AI Data Centers.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2025

Keeping up with Large Language Models: A Holistic Methodology of Compute, Memory, Communication, and Cost Modeling.
Proceedings of the IEEE International Symposium on Workload Characterization, 2025

2024
Bank on Compute-Near-Memory: Design Space Exploration of Processing-Near-Bank Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

Calibrating DRAMPower Model: A Runtime Perspective from Real-System HPC Measurements.
CoRR, 2024

2023
Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023

AMPeD: An Analytical Model for Performance in Distributed Training of Transformers.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

2022
Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Soft SIMD Based Energy Efficient Computing Microarchitecture.
CoRR, 2022

2021
Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2019
A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019


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