Karthikeyan Natarajan

According to our database, Karthikeyan Natarajan authored at least 11 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Novel Technique for Manufacturing, System-Level, and In-System Testing of Large SoC Using Functional Protocol-Based High-Speed I/O.

Amit Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal

IEEE Des. Test, August, 2023

2022

Novel Technique for Manufacturing & In-system Testing of Large Scale SoC using Functional Protocol Based High-Speed I/O.

Amit Pandey, Brendan Tully, Abhijeet Samudra, Ajay Nagarandal, Karthikeyan Natarajan, Rahul Singhal

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

High Speed IO Access for Test forms the foundation for Silicon Lifecycle Management.

Amit Pandey, Brendan Tully, Karthikeyan Natarajan

Proceedings of the IEEE International Test Conference, 2022

Comprehensive Power-Aware ATPG Methodology for Complex Low-Power Designs.

Khader S. Abdel-Hafez, Michael Dsouza, Likith Kumar Manchukonda, Elddie Tsai, Karthikeyan Natarajan, Ting-Pu Tai, Wenhao Hsueh, Smith Lai

Proceedings of the IEEE International Test Conference, 2022

Power Aware Test.

Likith Kumar Manchukonda, Karthikeyan Natarajan, Manish Arora

Proceedings of the IEEE European Test Symposium, 2022

2019

High Performance Graph Convolutional Networks with Applications in Testability Analysis.

Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Lossless Parallel Implementation of a Turbo Decoder on GPU.

Karthikeyan Natarajan, Nitin Chandrachoodan

Proceedings of the 25th IEEE International Conference on High Performance Computing, 2018

2016

A programmable method for low-power scan shift in SoC integrated circuits.

Ran Wang, Bonita Bhaskaran, Karthikeyan Natarajan, Ayub Abdollahian, Kaushik Narayanun, Krishnendu Chakrabarty, Amit Sanghani

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Dynamic docking architecture for concurrent testing and peak power reduction.

Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2015

Non-uniform DFT implementation for channel simulations in GPU.

Karthikeyan Natarajan, Nitin Chandrachoodan

Proceedings of the Twenty First National Conference on Communications, 2015

2011

Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips.

Amit Sanghani, Bo Yang, Karthikeyan Natarajan, Chunsheng Liu

Proceedings of the 29th IEEE VLSI Test Symposium, 2011