Sukanta Dey

Affiliations:
  • Indian Institute of Technology Guwahati, India


According to our database1, Sukanta Dey authored at least 15 papers between 2017 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2022
Secure Physical Design.
IACR Cryptol. ePrint Arch., 2022

2021
PGOpt: Multi-objective design space exploration framework for large-Scale on-chip power grid design in VLSI SoC using evolutionary computing technique.
Microprocess. Microsystems, 2021

Machine Learning for VLSI CAD: A Case Study in On-Chip Power Grid Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020
PGRDP: Reliability, Delay, and Power-Aware Area Minimization of Large-Scale VLSI Power Grid Network Using Cooperative Coevolution.
Proceedings of the Intelligent Computing Paradigm: Recent Trends, 2020

Machine Learning Approach for Fast Electromigration Aware Aging Prediction in Incremental Design of Large Scale On-chip Power Grid Network.
ACM Trans. Design Autom. Electr. Syst., 2020

ReFIT: Reliability Challenges and Failure Rate Mitigation Techniques for IoT Systems.
Proceedings of the Innovations for Community Services, 2020

Energy Efficient Approach to Detect Sinkhole Attack Using Roving IDS in 6LoWPAN Network.
Proceedings of the Innovations for Community Services, 2020

PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
RiverOpt: A Multiobjective Optimization Framework Based on Modified River Formation Dynamics Heuristic.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

JSpongeGen: A Pseudo Random Generator for Low Resource Devices.
Proceedings of the Distributed Computing and Internet Technology, 2019

StormOptimus: A Single Objective Constrained Optimizer Based on Brainstorming Process for VLSI Circuits.
Proceedings of the Brain Storm Optimization Algorithms: Concepts, 2019

2018
Minimizing area of VLSI power distribution networks using river formation dynamics.
J. Syst. Inf. Technol., 2018

PGIREM: Reliability-Constrained IR Drop Minimization and Electromigration Assessment of VLSI Power Grid Networks Using Cooperative Coevolution.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

EvadePDF: Towards Evading Machine Learning Based PDF Malware Classifiers.
Proceedings of the Security and Privacy - Second ISEA International Conference, 2018

2017
Markov Chain Model Using Lévy Flight for VLSI Power Grid Analysis.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017


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