Scott R. Cottier

According to our database, Scott R. Cottier authored at least 10 papers between 2005 and 2013.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2013

True hardware random number generation implemented in the 32-nm SOI POWER7+ processor.

John S. Liberty, Adrian Barrera, David W. Boerstler, Thomas B. Chadwick, Scott R. Cottier, H. Peter Hofstee, Julie A. Rosser, Marty L. Tsai

IBM J. Res. Dev., 2013

2008

Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V.

Juergen Pille, Chad Adams, Todd Christensen, Scott R. Cottier, Sebastian Ehrenreich, Fumihiro Kono, Daniel Nelson, Osamu Takahashi, Shunsako Tokito, Otto A. Torreiter, Otto Wagner, Dieter F. Wendel

IEEE J. Solid State Circuits, 2008

Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI.

Osamu Takahashi, Chad Adams, D. Ault, Erwin Behnen, O. Chiang, Scott R. Cottier, Paula K. Coulman, James Culp, Gilles Gervais, M. S. Gray, Y. Itaka, C. J. Johnson, Fumihiro Kono, L. Maurice, Kevin W. McCullen, Lam Nguyen, Y. Nishino, Hiromi Noro, Jürgen Pille, Mack W. Riley, M. Shen, Chiaki Takano, Shunsako Tokito, Tina Wagner, Hiroshi Yoshihara

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V.

Jürgen Pille, Chad Adams, Todd Christensen, Scott R. Cottier, Sebastian Ehrenreich, Fumihiro Kono, Daniel Nelson, Osamu Takahashi, Shunsako Tokito, Otto A. Torreiter, Otto Wagner, Dieter F. Wendel

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Cell Broadband Engine Processor Design Methodology.

Osamu Takahashi, Erwin Behnen, Scott R. Cottier, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, C. J. Johnson, Stephen D. Posluszny

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor.

Hwa-Joon Oh, Silvia M. Müller, Christian Jacobi, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong

IEEE J. Solid State Circuits, 2006

2005

Power-Conscious Design of the Cell Processor's Synergistic Processor Element.

Osamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman

IEEE Micro, 2005

Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor.

Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara

IEEE Micro, 2005

The circuit design of the synergistic processor element of a CELL processor.

Osamu Takahashi, Russ Cook, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Hwa-Joon Oh, S. Onish, Juergen Pille, Joel Silberman

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor.

Silvia M. Müller, Christian Jacobi, Hwa-Joon Oh, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong

Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005