Seong Joong Kim

According to our database1, Seong Joong Kim authored at least 20 papers between 2012 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Micro Bio Processor: a 0.144cc 70uW closed loop platform for body implant electroceutical systems.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
A 10-MHz 2-800-mA 0.5-1.5-V 90% Peak Efficiency Time-Based Buck Converter With Seamless Transition Between PWM/PFM Modes.
IEEE J. Solid State Circuits, 2018

Time-Based PWM Controller for Fully Integrated High Speed Switching DC-DC Converters - An Alternative to Conventional Analog and Digital Controllers.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017
A 2.4-GHz Ternary Sequence Spread Spectrum OOK Transceiver for Reliable and Ultra-Low Power Sensor Network Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 0.0021 mm<sup>2</sup> 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017

A 10MHz 2mA-800mA 0.5V-1.5V 90% peak efficiency time-based buck converter with seamless transition between PWM/PFM modes.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A 2.4GHz ternary sequence spread spectrum OOK transceiver with harmonic spur suppression and dual-mode detection architecture for ULP wearable devices.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

19.8 A 0.0021mm2 1.82mW 2.2GHz PLL using time-based integral control in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
A Highly Digital VCO-Based ADC Architecture for Current Sensing Applications.
IEEE J. Solid State Circuits, 2015

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method.
IEEE J. Solid State Circuits, 2015

A 4-Phase 30-70 MHz Switching Frequency Buck Converter Using a Time-Based Compensator.
IEEE J. Solid State Circuits, 2015

High Frequency Buck Converter Design Using Time-Based Control Techniques.
IEEE J. Solid State Circuits, 2015

A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

12.2 A1.8V 30-to-70MHz 87% peak-efficiency 0.32mm<sup>2</sup> 4-phase time-based buck converter consuming 3μA/MHz quiescent current in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement.
Proceedings of the Symposium on VLSI Circuits, 2014

A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW.
Proceedings of the Symposium on VLSI Circuits, 2014

A VCO-based current-to-digital converter for sensor applications.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2012
Challenges and directions of ultra low energy wireless sensor nodes for biosignal monitoring.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Ultra-low power sensor platform with wireless charging system.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012


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