Jianwang Zhai

Orcid: 0000-0002-1581-3536

Affiliations:

Beijing University of Posts and Telecommunications (BUPT), School of Integrated Circuits, Beijing, China
Tsinghua University, Beijing, China (former, pHd 2023)

According to our database¹, Jianwang Zhai authored at least 37 papers between 2021 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book In proceedings Article PhD thesis Dataset Other

Bibliography

2026

CHASE: A CHiplet Architecture Simulation and Exploration Framework with Decoupled Multi-Fidelity Optimization.

[BibT_eX]

[DOI]

Proceedings of the 2026 International Symposium on Physical Design, 2026

Performance Pragma-Based Design Space Pruning and Exploration for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

Etch-Explorer: A Robust Bayesian Optimization Framework for Stringent Constrained Plasma Etching.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2026, 2026

Structural Timing-Aware Circuit Partitioning with Feasibility Constraints for Multi-Chiplet Design.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2026, 2026

AutoShrink: Adaptive Search Space Shrinkage for Large-Scale Pareto Optimization of HLS Designs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2026

DynaOpt: A Heterogeneous Logic Optimization Framework with Dynamic Sequence Generation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2026

MAEDA: An LLM-Powered Multi-Agent Evaluation Framework for EDA Tool Documentation QA.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2026

HLS-Timer: Fine-Grained Path-Level Timing Estimation for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

Timing-Aware Optimization of Die-Level Routing and TDM Assignment for Multi-FPGA Systems.

[BibT_eX]

[DOI]

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

DrlGoFPGA: FPGA Global Placement Considering Input-Output Buffer Based on Deep Reinforcement Learning and Gradient Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025

FADiff: Fusion-Aware Differentiable Optimization for DNN Scheduling on Tensor Accelerators.

[BibT_eX]

[DOI]

CoRR, November, 2025

HieRFP: A Hierarchical Recognition and Floorplanning Framework for Reusable Modules.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

MILS: Modality Interaction Driven Learning for Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

AuxiliarySRAM: Exploring Elastic On-Chip Memory in 2.5D Chiplet Systems Design.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

WideGate: Beyond Directed Acyclic Graph Learning in Subcircuit Boundary Prediction.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2025

IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2025

Truly Pre-Routing Timing Prediction via Considering Power Delivery Network.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-Design.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop Prediction.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs.

[BibT_eX]

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

PIRLLS: Pretraining with Imitation and RL Finetuning for Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

The Survey of 2.5D Integrated Architecture: An EDA perspective.

[BibT_eX]

[DOI]

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., January, 2024

The Survey of Chiplet-based Integrated Architecture: An EDA perspective.

[BibT_eX]

[DOI]

CoRR, 2024

Effective Resource Model and Cost Scheme for Maze Routing in 3D Global Routing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

PolarGate: Breaking the Functionality Representation Bottleneck of And-Inverter Graph Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

PGAU: Static IR Drop Analysis for Power Grid using Attention U-Net Architecture and Label Distribution Smoothing.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Fast Estimation for Electromigration Nucleation Time Based on Random Activation Energy Model.

[BibT_eX]

[DOI]

Jingyu Jia

Jianwang Zhai

Kang Zhao

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Towards Automated RISC-V Microarchitecture Design with Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023

Microarchitecture Design Space Exploration via Pareto-Driven Active Learning.

[BibT_eX]

[DOI]

Jianwang Zhai

Yici Cai

IEEE Trans. Very Large Scale Integr. Syst., November, 2023

McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning.

[BibT_eX]

[DOI]

Jianwang Zhai

Yici Cai

Bei Yu

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2021

Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits.

[BibT_eX]

[DOI]

Jianwang Zhai

Yici Cai

Qiang Zhou

IEEE Trans. Circuits Syst. II Express Briefs, 2021

McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration Framework.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Jianwang Zhai

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