Mingfei Yu

Orcid: 0009-0009-6816-8903

According to our database1, Mingfei Yu authored at least 12 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2024
Unleashing the Power of T1-cells in SFQ Arithmetic Circuits.
CoRR, 2024

2023
Garbled Circuits Reimagined: Logic Synthesis Unleashes Efficient Secure Computation.
Cryptogr., September, 2023

SCP-SLAM: Accelerating DynaSLAM With Static Confidence Propagation.
Proceedings of the IEEE Conference Virtual Reality and 3D User Interfaces, 2023

Striving for Both Quality and Speed: Logic Synthesis for Practical Garbled Circuits.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Generating Lower-Cost Garbled Circuits: Logic Synthesis Can Help.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

2022
Parallel Scheduling Attention Mechanism: Generalization and Optimization.
IPSJ Trans. Syst. LSI Des. Methodol., 2022

Low-Precision Quantization Techniques for Hardware-Implementation-Friendly BERT Models.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

2021
Loop Closure Detection by Using Global and Local Features With Photometric and Viewpoint Invariance.
IEEE Trans. Image Process., 2021


Logic Synthesis for Generalization and Learning Addition.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

A Decomposition-Based Synthesis Algorithm for Sparse Matrix-Vector Multiplication in Parallel Communication Structure.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Parallel Scheduling Self-attention Mechanism: Generalization and Optimization.
CoRR, 2020


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