Hideki Takase

Orcid: 0000-0002-2660-5927

According to our database1, Hideki Takase authored at least 34 papers between 2008 and 2023.

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Bibliography

2023
Memory-saving LDoS Attacker Detection Algorithms in Zigbee Network.
J. Inf. Process., 2023

ILP Based Mapping for Elastic CGRAs.
Proceedings of the 29th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2023

An Area-Efficient Coarse-Grained Reconfigurable Array Design for Approximate Computing.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Performance Modeling and Scalability Analysis of Stream Computing in ESSPER FPGA Clusters.
Proceedings of the International Conference on Field Programmable Technology, 2023

Resource Allocation Methods among Server Clusters in a Resource Permeating Distributed Computing Platform for 5G Networks.
Proceedings of the 47th IEEE Annual Computers, Software, and Applications Conference, 2023

An asynchronous federated learning focusing on updated models for decentralized systems with a practical framework.
Proceedings of the 47th IEEE Annual Computers, Software, and Applications Conference, 2023

F2MKD: Fog-enabled Federated Learning with Mutual Knowledge Distillation.
Proceedings of the 20th IEEE Consumer Communications & Networking Conference, 2023

2022
Elastic Sample Filter: An FPGA-based Accelerator for Bayesian Network Structure Learning.
Proceedings of the International Conference on Field-Programmable Technology, 2022

2021
LDoS Attacker Detection Algorithms in Zigbee Network.
Proceedings of the 2021 IEEE International Conferences on Internet of Things (iThings) and IEEE Green Computing & Communications (GreenCom) and IEEE Cyber, 2021

Zytlebot : FPGA integrated ros-based autonomous mobile robot.
Proceedings of the International Conference on Field-Programmable Technology, 2021

2020
mROS: A Lightweight Runtime Environment of ROS 1 nodes for Embedded Devices.
J. Inf. Process., 2020

An FPGA Accelerator for Bayesian Network Structure Learning with Iterative Use of Processing Elements.
Proceedings of the International Conference on Field-Programmable Technology, 2020

2019
ZytleBot: FPGA Integrated Development Platform for ROS Based Autonomous Mobile Robot.
Proceedings of the International Conference on Field-Programmable Technology, 2019

mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices.
Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

ZytleBot: FPGA Integrated Development Platform for ROS Based Autonomous Mobile Robot.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

A concept of a hardware design environment with the functional language elixir: work-in-progress.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis Companion, 2019

2018
A Study on Introducing FPGA to ROS Based Autonomous Driving System.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Design concept of a lightweight runtime environment for robot software components onto embedded devices: work-in-progress.
Proceedings of the International Conference on Embedded Software, 2018

2016
An evaluation framework of OS-level power managements for the big.LITTLE architecture.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2015
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems.
IPSJ Trans. Syst. LSI Des. Methodol., 2015

2014
An Integrated Framework for Energy Optimization of Embedded Real-Time Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

2013
A Buffering Method for Parallelized Loop with Non-Uniform Dependencies in High-Level Synthesis.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

2012
Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework.
IPSJ Trans. Syst. LSI Des. Methodol., 2012

2011
Partitioning and Allocation of Scratch-Pad Memory for Energy Minimization of Priority-Based Preemptive Multi-Task Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

An integrated optimization framework for reducing the energy consumption of embedded real-time applications.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Checkpoint Extraction Using Execution Traces for Intra-task DVFS in Embedded Systems.
Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

2010
Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems.
Proceedings of the Design, Automation and Test in Europe, 2010

Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems.
Proceedings of the 2010 International Conference on Compilers, 2010

2009
Partitioning and Allocation of Scratch-Pad Memory in Priority-Based Multi-Task Systems.
IPSJ Trans. Syst. LSI Des. Methodol., 2009

History of summer school on embedded system technologies organized by students and young engineers.
Proceedings of the 2009 Workshop on Embedded Systems Education, 2009

2008
Energy efficiency of scratch-pad memory in deep submicron domains: an empirical study.
IEICE Electron. Express, 2008

Energy Efficiency of Scratch-Pad Memory at 65 nm and Below: An Empirical Study.
Proceedings of the International Conference on Embedded Software and Systems, 2008


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