Shunyang Bi

According to our database, Shunyang Bi authored at least 5 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2026

An Efficient Optimization Framework for Netlist Partitioning by Co-optimizing Moves and Replications.

Qiwang Chen, Hailong You, Shunyang Bi, Zehong Wei

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2024

MaPart: An Efficient Multi-FPGA System-Aware Hypergraph Partitioning Framework.

Benzheng Li, Shunyang Bi, Hailong You, Zhongdong Qi, Guangxin Guo, Richard Sun, Yuming Zhang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort.

Johann Knechtel, Mohammad Eslami, Peng Zou, Min Wei, Xingyu Tong, Binggang Qiu, Zhijie Cai, Guohao Chen, Benchao Zhu, Jiawei Li, Jun Yu, Jianli Chen, Chun-Wei Chiu, Min-Feng Hsieh, Chia-Hsiu Ou, Ting-Chi Wang, Bangqi Fu, Qijing Wang, Yang Sun, Qin Luo, Anthony W. H. Lau, Fangzhou Wang, Evangeline F. Y. Young, Shunyang Bi, Guangxin Guo, Haonan Wu, Zhengguang Tang, Hailong You, Cong Li, Ramesh Karri, Ozgur Sinanoglu, Samuel Pagliarini

IACR Cryptol. ePrint Arch., 2024

TopoOrderPart: a Multi-level Scheduling-Driven Partitioning Framework for Processor-Based Emulation.

Shunyang Bi, Jing Tang, Hailong You, Haonan Wu, Cong Li, Richard Sun

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

An Efficient Hypergraph Partitioner under Inter - Block Interconnection Constraints.

Benzheng Li, Hailong You, Shunyang Bi, Yuming Zhang

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024