Hailong You

Orcid: 0000-0003-3427-5320

According to our database1, Hailong You authored at least 24 papers between 2009 and 2026.

Collaborative distances:

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Accurate Analytic Equation Generation for Compact Modeling with Physics-Assisted Kolmogorov-Arnold Networks.
ACM Trans. Design Autom. Electr. Syst., July, 2026

Multi-objective k-way parallel hypergraph partitioning with proximal gradient algorithm.
Comput. Optim. Appl., April, 2026

A deep learning based global I-V and C-V parameter extractor for BSIM-CMG.
Microelectron. J., 2026

A novel hybrid MFMIS-MFIS NC-CFET with stepped channels for enhanced capacitance matching and performance.
Microelectron. J., 2026

An Efficient Optimization Framework for Netlist Partitioning by Co-optimizing Moves and Replications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
Challenges and Solutions in Spectrum Management for Direct Satellite-to-Device Communication.
IEEE Commun. Mag., November, 2025

A Multi-Level Framework for Multi-Objective Hypergraph Partitioning: Combining Minimum Spanning Tree and Proximal Gradient.
CoRR, September, 2025

Knowledge transferring framework for cell library characterization.
Microelectron. J., 2025

A blockchain-based resource sharing incentivization mechanism for multi-to-multi in compute first networking.
Comput. Networks, 2025

2024
MaPart: An Efficient Multi-FPGA System-Aware Hypergraph Partitioning Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024

Semi-Supervised Transfer Learning Framework for Aging-Aware Library Characterization.
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024

Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort.
IACR Cryptol. ePrint Arch., 2024

TopoOrderPart: a Multi-level Scheduling-Driven Partitioning Framework for Processor-Based Emulation.
Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

An Efficient Hypergraph Partitioner under Inter - Block Interconnection Constraints.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

A High Performance Detailed Router Based on Integer Programming with Adaptive Route Guides.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
A novel inverted T-shaped negative capacitance TFET for label-free biosensing application.
Microelectron. J., September, 2023

Machine Learning Based Framework for Fast Resource Estimation of RTL Designs Targeting FPGAs.
ACM Trans. Design Autom. Electr. Syst., March, 2023

ASSURER: A PPA-friendly Security Closure Framework for Physical Design.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
High quality hypergraph partitioning for logic emulation.
Integr., 2022

Effective and Efficient Detailed Routing with Adaptive Rip-up Scheme and Pin Access Refinement.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
Placement for Wafer-Scale Deep Learning Accelerator.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2015
Yield-Based Capability Index for Evaluating the Performance of Multivariate Manufacturing Process.
Qual. Reliab. Eng. Int., 2015

2014
A <i>t</i>-chart for Monitoring Multi-variety and Small Batch Production Run.
Qual. Reliab. Eng. Int., 2014

2009
Kriging Model combined with latin hypercube sampling for surrogate modeling of analog integrated circuit performance.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009


  Loading...