Soumya Eachempati

According to our database1, Soumya Eachempati authored at least 12 papers between 2007 and 2013.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays.
ACM J. Emerg. Technol. Comput. Syst., 2013

2011
RAFT: A router architecture with frequency tuning for on-chip networks.
J. Parallel Distributed Comput., 2011

Automated mapping for reconfigurable single-electron transistor arrays.
Proceedings of the 48th Design Automation Conference, 2011

2010
Optimizing power and performance for reliable on-chip networks.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect.
IET Circuits Devices Syst., 2009

Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

A case for dynamic frequency tuning in on-chip networks.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2008
Reconfigurable BDD based quantum circuits.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

MIRA: A Multi-layered On-Chip Interconnect Router Architecture.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2007
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Assessing carbon nanotube bundle interconnect for future FPGA architectures.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007


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