Niranjan Soundararajan

According to our database1, Niranjan Soundararajan authored at least 14 papers between 2005 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Dynamic Power Budgeting for Mobile Systems Running Graphics Workloads.
IEEE Trans. Multi-Scale Computing Systems, 2018

2017
User-aware Frame Rate Management in Android Smartphones.
ACM Trans. Embedded Comput. Syst., 2017

2015
VIP: virtualizing IP chains on handheld platforms.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Domain knowledge based energy management in handhelds.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014
GemDroid: a framework to evaluate mobile platforms.
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

Short-Circuiting Memory Traffic in Handheld Platforms.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2011
Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
Characterizing the soft error vulnerability of multicores running multithreaded applications.
Proceedings of the SIGMETRICS 2010, 2010

Optimizing power and performance for reliable on-chip networks.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2008
Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Analysis and solutions to issue queue process variation.
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

2007
Mechanisms for bounding vulnerabilities of processor structures.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

2006
PASCOM: Power Model for Supercomputers.
Proceedings of the Architecture of Computing Systems, 2006

2005
Memory In Processor-Supercomputer On a Chip: Processor Design and Execution Semantics for Massive Single-Chip Performance.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005


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