Steven Bartling

According to our database, Steven Bartling authored at least 10 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

16MHz FRAM Micro-Controller with a Low-Cost Sub-1μA Embedded Piezo-Electric Strain Sensor for ULP Motion Detection.

Sudhanshu Khanna, Michael Zwerg, Brian Elies, Juergen Luebbe, Nagaraj Krishnasawamy, Hadi Najar, Suman Bellary, Wei-Yan Shih, Scott R. Summerfelt, Steven Bartling

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

Energy Efficient Adiabatic FRAM with 0.99 PJ/Bit Write for IoT Applications.

Supreet Jeloka, Zhehong Wang, Ruochen Xie, Sudhanshu Khanna, Steven Bartling, Dennis Sylvester, David T. Blaauw

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017

Non-volatile logic SoC with software-hardware co-design and integrated supply supervisor for energy harvesting applications.

Michael Zwerg, Sudhanshu Khanna, Steven Bartling

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

FAR: A 4.12μW ferro-electric auto-recovery for battery-less BSN SoCs.

Farah B. Yahya, Christopher J. Lukas, Benton H. Calhoun, Steven Bartling

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2015

A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU.

Kaushik Mazumdar, Steven Bartling, Sudhanshu Khanna, Mircea R. Stan

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014

An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at <i>VDD</i> = 0 V Achieving Zero Leakage With < 400-ns Wakeup Time for ULP Applications.

Sudhanshu Khanna, Steven Bartling, Michael Clinton, Scott R. Summerfelt, John A. Rodriguez, Hugh P. McAdams

IEEE J. Solid State Circuits, 2014

A 1.2µW SIMO energy harvesting and power management unit with constant peak inductor current control achieving 83-92% efficiency across wide input and output voltages.

Aatmesh Shrivastava, Yogesh K. Ramadass, Sudhanshu Khanna, Steven Bartling, Benton H. Calhoun

Proceedings of the Symposium on VLSI Circuits, 2014

2013

An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at VDD=0V with <400ns wakeup and sleep transitions.

Steven Bartling, Sudhanshu Khanna, Michael Clinton, Scott R. Summerfelt, John A. Rodriguez, Hugh P. McAdams

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

A Low-Voltage 1 Mb FRAM in 0.13 µm CMOS Featuring Time-to-Digital Sensing for Expanded Operating Margin.

Masood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2012

2011

A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS.

Masood Qazi, Michael Clinton, Steven Bartling, Anantha P. Chandrakasan

Proceedings of the IEEE International Solid-State Circuits Conference, 2011