Sudhanshu Khanna
According to our database1,
Sudhanshu Khanna
authored at least 18 papers
between 2009 and 2019.
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Bibliography
2019
16MHz FRAM Micro-Controller with a Low-Cost Sub-1μA Embedded Piezo-Electric Strain Sensor for ULP Motion Detection.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
2017
Non-volatile logic SoC with software-hardware co-design and integrated supply supervisor for energy harvesting applications.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2015
A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
2014
An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at <i>VDD</i> = 0 V Achieving Zero Leakage With < 400-ns Wakeup Time for ULP Applications.
IEEE J. Solid State Circuits, 2014
A 32 b 90 nm Processor Implementing Panoptic DVS Achieving Energy Efficient Operation From Sub-Threshold to High Performance.
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
A 1.2µW SIMO energy harvesting and power management unit with constant peak inductor current control achieving 83-92% efficiency across wide input and output voltages.
Proceedings of the Symposium on VLSI Circuits, 2014
2013
An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at VDD=0V with <400ns wakeup and sleep transitions.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
An analytical model for performance yield of nanoscale SRAM accounting for the sense amplifier strobe signal.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
A 90nm data flow processor demonstrating fine grained DVS for energy efficient operation from 0.25V to 1.2V.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Sub-threshold Operation and Cross-hierarchy Design for Ultra Low Power Wearable Sensors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009