Jeyanandh Paramesh

According to our database, Jeyanandh Paramesh authored at least 49 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A 46.6 μg/√Hz Single-Chip Accelerometer Exploiting a DTC-Assisted Chopper Amplifier.

Xiaoliang Li, Vincent P. J. Chung, Metin G. Guney, Tamal Mukherjee, Gary K. Fedder, Jeyanandh Paramesh

IEEE J. Solid State Circuits, February, 2024

2023

A mm-wave RC PPF Quadrature Network with Gain Boosting in 22nm CMOS FDSOI.

Mohammad Ghaedi Bardeh, Navid Naseh, Jierui Fu, Jeyanandh Paramesh, Kamran Entesari

Proceedings of the IEEE Radio and Wireless Symposium, 2023

An Efficient Meta-Reinforcement Learning Approach for Circuit Linearity Calibration via Style Injection.

Chao Rong, Jeyanandh Paramesh, L. Richard Carley

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022

A Deep Reinforcement Learning Framework for High-Dimensional Circuit Linearization.

Chao Rong, Jeyanandh Paramesh, L. Richard Carley

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Dual-Band, Two-Layer Millimeter-Wave Transceiver for Hybrid MIMO Systems.

Susnata Mondal, Larry Richard Carley, Jeyanandh Paramesh

IEEE J. Solid State Circuits, 2022

2020

Power-Efficient Design Techniques for mm-Wave Hybrid/Digital FDD/Full-Duplex MIMO Transceivers.

Susnata Mondal, Jeyanandh Paramesh

IEEE J. Solid State Circuits, 2020

A Reconfigurable High-Bandwidth CMOS-MEMS Capacitive Accelerometer Array with High-g Measurement Capability and Low Bias Instability.

Xiaoliang Li, Vincent P. J. Chung, Metin G. Guney, Tamal Mukherjee, Gary K. Fedder, Jeyanandh Paramesh

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

High-g Capacitive Accelerometer Arrays with Low Bias Instability.

Gary K. Fedder, Vincent P. J. Chung, Metin G. Guney, Xiaoliang Li, Yi-Chung Lin, Suresh Santhanam, Jeyanandh Paramesh, Tamal Mukherjee

Proceedings of the IEEE/ION Position, Location and Navigation Symposium, 2020

Millimeter-wave full duplex radios.

Vaibhav Singh, Susnata Mondal, Akshay Gadre, Milind Srivastava, Jeyanandh Paramesh, Swarun Kumar

Proceedings of the MobiCom '20: The 26th Annual International Conference on Mobile Computing and Networking, 2020

4.4 A 28/37GHz Scalable, Reconfigurable Multi-Layer Hybrid/Digital MIMO Transceiver for TDD/FDD and Full-Duplex Communication.

Susnata Mondal, L. Richard Carley, Jeyanandh Paramesh

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019

An 18 nW -47/-40 dBm Sensitivity 3/100 kbps MEMS-Assisted CMOS Wake-Up Receiver.

Mazen Soliman, Abhay Kochhar, Hoda Abdelsalam, Flavius V. Pop, Gabriel Vidal-Álvarez, Jeffrey A. Weldon, Gianluca Piazza, Jeyanandh Paramesh

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Reconfigurable 28-/37-GHz MMSE-Adaptive Hybrid-Beamforming Receiver for Carrier Aggregation and Multi-Standard MIMO Communication.

Susnata Mondal, Jeyanandh Paramesh

IEEE J. Solid State Circuits, 2019

A Reconfigurable Bidirectional 28/37/39GHz Front-End Supporting MIMO-TDD, Carrier Aggregation TDD and FDD/Full-Duplex with Self-Interference Cancellation in Digital and Fully Connected Hybrid Beamformers.

Susnata Mondal, Rahul Singh, Jeyanandh Paramesh

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A High Dynamic Range CMOS-MEMS Accelerometer Array with Drift Compensation and Fine-Grain Offset Compensation.

Xiaoliang Li, Vincent P. J. Chung, Metin G. Guney, Tamal Mukherjee, Gary K. Fedder, Jeyanandh Paramesh

Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018

Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs.

Shaolong Liu, Taimur Gibran Rabuske, Jeyanandh Paramesh, Lawrence T. Pileggi, Jorge R. Fernandes

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 25-30 GHz Fully-Connected Hybrid Beamforming Receiver for MIMO Communication.

Susnata Mondal, Rahul Singh, Ahmed I. Hussein, Jeyanandh Paramesh

IEEE J. Solid State Circuits, 2018

A 450 fs 65-nm CMOS Millimeter-Wave Time-to-Digital Converter Using Statistical Element Selection for All-Digital PLLs.

Ahmed I. Hussein, Sriharsha Vasadi, Jeyanandh Paramesh

IEEE J. Solid State Circuits, 2018

802.11g/n Compliant Fully Integrated Wake-Up Receiver With -72-dBm Sensitivity in 14-nm FinFET CMOS.

Erkan Alpman, Ahmad Khairi, Richard Dorrance, Minyoung Park, V. Srinivasa Somayazulu, Jeffrey R. Foerster, Ashoke Ravi, Jeyanandh Paramesh, Stefano Pellerano

IEEE J. Solid State Circuits, 2018

A reconfigurable 28/37GHz hybrid-beamforming MIMO receiver with inter-band carrier aggregation and RF-domain LMS weight adaptation.

Susnata Mondal, Rahul Singh, Jeyanandh Paramesh

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 125 MS/s 10.4 ENOB 10.1 fJ/Conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS.

Shaolong Liu, Jeyanandh Paramesh, Larry T. Pileggi, Taimur Gibran Rabuske, Jorge Fernandcs

Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017

Frequency-Channelized Mismatch-Shaped Quadrature Data Converters for Carrier Aggregation in MU-MIMO LTE-A.

Sandipan Kundu, Subhanshu Gupta, David J. Allstot, Jeyanandh Paramesh

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 50-66-GHz Phase-Domain Digital Frequency Synthesizer With Low Phase Noise and Low Fractional Spurs.

Ahmed I. Hussein, Sriharsha Vasadi, Jeyanandh Paramesh

IEEE J. Solid State Circuits, 2017

Design and Self-Calibration Techniques for Inductor-Less Millimeter-Wave Frequency Dividers.

Ahmed I. Hussein, Jeyanandh Paramesh

IEEE J. Solid State Circuits, 2017

19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fsrms jitter.

Ahmed I. Hussein, Sriharsha Vasadi, Mazen Soliman, Jeyanandh Paramesh

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A four-antenna baseband multipath emulator for millimeter-wave channels.

Mazen Soliman, Shih-Chang Hung, Jeyanandh Paramesh

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2015

A 1.2 V 2.64 GS/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN.

Sandipan Kundu, Erkan Alpman, Julia Hsin-Lin Lu, Hasnain Lakdawala, Jeyanandh Paramesh, Byunghoo Jung, Sarit Zur, Eshel Gordon

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Compact, Supply-Voltage Scalable 45-66 GHz Baseband-Combining CMOS Phased-Array Receiver.

Sandipan Kundu, Jeyanandh Paramesh

IEEE J. Solid State Circuits, 2015

DAC mismatch shaping for quadrature sigma-delta data converters.

Sandipan Kundu, Subhanshu Gupta, David J. Allstot, Jeyanandh Paramesh

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Statistical Learning in Chip (SLIC).

Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Adaptive Beamforming Assisted Decision Feedback Equalization for Millimeter Wave Receivers.

Ahmed I. Hussein, Sandipan Kundu, Jeyanandh Paramesh

Proceedings of the 2015 IEEE Global Communications Conference, 2015

A 10 mW 60GHz 65nm CMOS DCO with 24% tuning range and 40 kHz frequency granularity.

Ahmed I. Hussein, Shadi Saberi, Jeyanandh Paramesh

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

SLIC: Statistical learning in chip.

Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN.

Sandipan Kundu, Julia Hsin-Lin Lu, Erkan Alpman, Hasnain Lakdawala, Jeyanandh Paramesh, Byunghoo Jung, Sarit Zur, Eshel Gordon

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

A stepped-frequency continuous wave ranger for aiding pedestrian navigation.

James Downey, Jeyanandh Paramesh, Daniel D. Stancil, Tamal Mukherjee

Proceedings of the IEEE Topical Conference on Wireless Sensors and Sensor Networks, 2013

Ultra-low power frequency and duty-cycle modulated implantable pressure-temperature sensor.

Ahmad Khairi, Chenyang Wu, Yoed Rabin, Gary K. Fedder, Jeyanandh Paramesh, David Schwartzman

Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

2012

Multi-rate Polyphase DSP and LMS Calibration Schemes for Oversampled ADCs.

Subhanshu Gupta, Yi Tang, Jeyanandh Paramesh, David J. Allstot

J. Signal Process. Syst., 2012

Low-power front-end amplification and frequency generation techniques for ultra-wideband millimeter-wave transceivers.

Jeyanandh Paramesh, Sandipan Kundu, Shadi Saberi

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

A supply-voltage scalable, 45 nm CMOS ultra-wideband receiver for mm-wave ranging and communication.

Sandipan Kundu, Ahmad Khairi, Jeyanandh Paramesh

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

Multi-rate polyphase DSP and LMS calibration schemes for oversampled data conversion systems.

Subhanshu Gupta, Yi Tang, Kuang-Wei Cheng, Jeyanandh Paramesh, David J. Allstot

Proceedings of the IEEE International Conference on Acoustics, 2011

Post-silicon calibration of analog CMOS using phase-change memory cells.

Cheng-Yuan Wen, Jeyanandh Paramesh, Larry T. Pileggi, Jing Li, SangBum Kim, Jonathan E. Proesel, Chung Lam

Proceedings of the 37th European Solid-State Circuits Conference, 2011

2009

Integrated Quadrature Couplers and Their Application in Image-Reject Receivers.

Dicle Ozis, Jeyanandh Paramesh, David J. Allstot

IEEE J. Solid State Circuits, 2009

2008

Cascaded Complex ADCs With Adaptive Digital Calibration for I/Q Mismatch.

Yi Tang, Kuang-Wei Cheng, Subhanshu Gupta, Jeyanandh Paramesh, David J. Allstot

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Hybrid modeling techniques for low OSR cascade continuous-time SigmaDelta modulators.

Subhanshu Gupta, Yi Tang, David J. Allstot, Jeyanandh Paramesh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

A Digital-Summing Feedforward Sigma-Delta Modulator and its Application to a Cascade ADC.

Yi Tang, Subhanshu Gupta, Jeyanandh Paramesh, David J. Allstot

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Analysis of the Bridged T-Coil Circuit Using the Extra-Element Theorem.

Jeyanandh Paramesh, David J. Allstot

IEEE Trans. Circuits Syst. II Express Briefs, 2006

A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion.

Mostafa Elmala, Jeyanandh Paramesh, Krishnamurthy Soumyanath

IEEE J. Solid State Circuits, 2006

Analysis and design of lumped-element quadrature couplers with lossy passive elements.

Dicle Ozis, Jeyanandh Paramesh, David J. Allstot

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity.

Jeyanandh Paramesh, Ralph Bishop, Krishnamurthy Soumyanath, David J. Allstot

IEEE J. Solid State Circuits, 2005

2001

Use of sigma-delta modulation to control EMI from switch-mode power supplies.

Jeyanandh Paramesh, Annette R. von Jouanne

IEEE Trans. Ind. Electron., 2001