Tai Song

According to our database, Tai Song authored at least 14 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Hardened latch designs based on the characteristic of transistor for mitigating multiple-node-upsets in harsh radiation environments.

Hui Xu, Chaoming Liu, Ruijun Ma, Tai Song, Zhengfeng Huang, Jun Wang, Xuewei Qin, Yu Xia

Microelectron. J., January, 2024

2023

Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix.

Zhengfeng Huang, Dongxing Ma, Runwu Ji, Huaguo Liang, Aibin Yan, Tai Song, Tianming Ni

IEEE Trans. Aerosp. Electron. Syst., December, 2023

Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation.

Tai Song, Zhengfeng Huang, Xiaohui Guo, Krstic Milos

J. Electron. Test., April, 2023

Linear regression combined KNN algorithm to identify latent defects for imbalance data of ICs.

Liang Huang, Tai Song, Tiezhen Jiang

Microelectron. J., 2023

2022

RLDA: Valid test pattern identification by machine learning classification method for VLSI test.

Tai Song, Zhengfeng Huang, Xiaohui Guo

Microelectron. J., 2022

VLSI test through an improved LDA classification algorithm for test cost reduction.

Liang Huang, Tai Song

Microelectron. J., 2022

Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements.

Zhengfeng Huang, Wanshu Zhong, Lanxi Duan, Yue Zhang, Huaguo Liang, Jianan Wang, Tai Song, Yingchun Lu

J. Circuits Syst. Comput., 2022

A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications.

Aibin Yan, Kuikui Qian, Tai Song, Zhengfeng Huang, Tianming Ni, Yu Chen, Xiaoqing Wen

Integr., 2022

Valid test pattern identification for VLSI adaptive test.

Tai Song, Tianming Ni, Zhengfeng Huang, Jinlei Wan

Integr., 2022

Machine learning classification algorithm for VLSI test cost reduction.

Tai Song, Zhengfeng Huang, Aibin Yan

Integr., 2022

2021

Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs.

Tai Song, Huaguo Liang, Zhengfeng Huang, Tianming Ni, Ying Sun

IEICE Electron. Express, 2021

2020

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC.

Tianming Ni, Hao Chang, Tai Song, Qi Xu, Zhengfeng Huang, Huaguo Liang, Aibin Yan, Xiaoqing Wen

IEEE Trans. Circuits Syst., 2020

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm.

Tai Song, Huaguo Liang, Tianming Ni, Zhengfeng Huang, Yingchun Lu, Jinlei Wan, Aibin Yan

IEEE Access, 2020

2019

Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory.

Tai Song, Huaguo Liang, Ying Sun, Zhengfeng Huang, Maoxiang Yi, Xiangsheng Fang, Aibin Yan

Proceedings of the 37th IEEE VLSI Test Symposium, 2019