Maoxiang Yi

According to our database, Maoxiang Yi authored at least 38 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

High-efficiency TRNG Design Based on Multi-bit Dual-ring Oscillator.

Yingchun Lu, Yun Yang, Rong Hu, Huaguo Liang, Maoxiang Yi, Zhengfeng Huang, Yuanming Ma, Tian Chen, Liang Yao

ACM Trans. Reconfigurable Technol. Syst., December, 2023

Design of approximate Booth multipliers based on error compensation.

Yongxia Sheng, Huaguo Liang, Bao Fang, Cuiyun Jiang, Zhengfeng Huang, Maoxiang Yi, Yingchun Lu

Integr., May, 2023

A dynamically reconfigurable entropy source circuit for high-throughput true random number generator.

Liyu Jin, Maoxiang Yi, Yuan Xiao, Lifa Sun, Yingchun Lu, Huaguo Liang

Microelectron. J., March, 2023

Improvement of cell internal weak defects detection under process variation by optimizing test path and test pattern.

Hong Zhang, Huaguo Liang, Jiewen Hu, Zhiwei Shao, Maoxiang Yi, Yingchun Lu, Zhengfeng Huang

Microelectron. J., 2023

2022

Design of True Random Number Generator Based on Multi-Stage Feedback Ring Oscillator.

Jianguo Cui, Maoxiang Yi, Di Cao, Liang Yao, Xinyu Wang, Huaguo Liang, Zhengfeng Huang, Haochen Qi, Tianming Ni, Yingchun Lu

IEEE Trans. Circuits Syst. II Express Briefs, 2022

M-RO PUF: A portable pure digital RO PUF based on MUX unit.

Liang Yao, Huaguo Liang, Qian Han, Hong Zhang, Zhengfeng Huang, Cuiyun Jiang, Maoxiang Yi, Yingchun Lu

Microelectron. J., 2022

A reconfigurable PUF structure with dual working modes based on entropy separation model.

Yanjie Wang, Huaguo Liang, Yuchuan Wang, Liang Yao, Maoxiang Yi, Zhengfeng Huang, Yingchun Lu

Microelectron. J., 2022

A reconfigurable test method based on LFSR for 3D stacking integrated circuits.

Chen Tian, Jianyong Lu, Liu Jun, Huaguo Liang, Yingchun Lu, Maoxiang Yi

Integr., 2022

A Low Power-Consumption Triple-Node-Upset-Tolerant Latch Design.

Yingchun Lu, Guangzhen Hu, Jianan Wang, Hao Wang, Liang Yao, Huaguo Liang, Maoxiang Yi, Zhengfeng Huang

J. Electron. Test., 2022

A Lightweight M_TRNG Design based on MUX Cell Entropy using Multiphase Sampling.

Liang Yao, Huaguo Liang, Hong Zhang, Tianming Ni, Maoxiang Yi, Yingchun Lu

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

2021

Pure Digital Scalable Mixed Entropy Separation Structure for Physical Unclonable Function and True Random Number Generator.

Yingchun Lu, Xinyu Wang, Yanjie Wang, Yuan Zhang, Liang Yao, Maoxiang Yi, Zhengfeng Huang, Huaguo Liang

IEEE Trans. Very Large Scale Integr. Syst., 2021

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure.

Xinyu Wang, Huaguo Liang, Yanjie Wang, Liang Yao, Yang Guo, Maoxiang Yi, Zhengfeng Huang, Haochen Qi, Yingchun Lu

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A high reliability physically unclonable function based on multiple tunable ring oscillator.

Yuan Zhang, Huaguo Liang, Liang Yao, Maoxiang Yi, Zhengfeng Huang, Yingchun Lu

Microelectron. J., 2021

Approximate multipliers based on a novel unbiased approximate 4-2 compressor.

Bao Fang, Huaguo Liang, Dawen Xu, Maoxiang Yi, Yongxia Sheng, Cuiyun Jiang, Zhengfeng Huang, Yingchun Lu

Integr., 2021

2020

Jitter-Quantizing-Based TRNG Robust Against PVT Variations.

Yingchun Lu, Huaguo Liang, Liang Yao, Xinyu Wang, Haochen Qi, Maoxiang Yi, Cuiyun Jiang, Zhengfeng Huang

IEEE Access, 2020

2019

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application.

Aibin Yan, Kang Yang, Zhengfeng Huang, Jiliang Zhang, Jie Cui, Xiangsheng Fang, Maoxiang Yi, Xiaoqing Wen

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Pulse Shrinking-Based Test Solution for Prebond Through Silicon via in 3-D ICs.

Maoxiang Yi, Jingchang Bian, Tianming Ni, Cuiyun Jiang, Hao Chang, Huaguo Liang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory.

Tai Song, Huaguo Liang, Ying Sun, Zhengfeng Huang, Maoxiang Yi, Xiangsheng Fang, Aibin Yan

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2018

Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique.

Aibin Yan, Zhile Chen, Zhengfeng Huang, Xiangsheng Fang, Maoxiang Yi, Jing Guo

Proceedings of the IEEE International Test Conference in Asia, 2018

A High Reliability FPGA Chip Identification Generator Based on PDLs.

Kai Zhou, Huaguo Liang, Yue Jiang, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yao Yao

Proceedings of the 27th IEEE Asian Test Symposium, 2018

Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOS.

Aibin Yan, Yafei Ling, Kang Yang, Zhili Chen, Maoxiang Yi

Proceedings of the 27th IEEE Asian Test Symposium, 2018

An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs.

Xiumin Xu, Huaguo Liang, Kai Zhou, Gaoliang Ma, Zhengfeng Huang, Maoxiang Yi, Tianming Ni, Yingchun Lu

Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Low-Cost High-Efficiency True Random Number Generator on FPGAs.

Gaoliang Ma, Huaguo Liang, Liang Yao, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Kai Zhou

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.

Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yiming Ouyang, Huaguo Liang

IEEE Trans. Very Large Scale Integr. Syst., 2017

An Output-Capacitorless Ultra-Low Power Low-Dropout Regulator.

Xin Cheng, Hongyu Liang, Longjie Du, Zhang Zhang, Maoxiang Yi, Guangjun Xie

J. Circuits Syst. Comput., 2017

A highly reliable butterfly PUF in SRAM-based FPGAs.

Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xiangsheng Fang, Tianming Ni, Maoxiang Yi

IEICE Electron. Express, 2017

A single event transient detector in SRAM-based FPGAs.

Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yingchun Lu, Aibin Yan, Tianming Ni, Maoxiang Yi

IEICE Electron. Express, 2017

HLDTL: High-performance, low-cost, and double node upset tolerant latch design.

Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Jie Cui, Huaguo Liang

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016

Co-mitigating circuit PBTI and HCI aging considering NMOS transistor stacking effect.

Maoxiang Yi, Yingxian Gan, Zhengfeng Huang, Huaguo Liang

Proceedings of the International Symposium on Integrated Circuits, 2016

NBTI mitigation by M-IVC with input duty cycle and randomness constraints.

Maoxiang Yi, Xiaohong Liu, Qingwu Wu, Tianming Ni, Zhengfeng Huang, Huaguo Liang

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

2015

A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology.

Aibin Yan, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Maoxiang Yi

IEICE Trans. Electron., 2015

NBTI-induced circuit aging optimization by protectability-aware gate replacement technique.

Guimao Zhang, Maoxiang Yi, Yong Miao, Dawen Xu, Huaguo Liang

Proceedings of the 16th Latin-American Test Symposium, 2015

MTTF-Aware Reliability Task Scheduling for Heterogeneous Multicore System.

Huaguo Liang, Yangyang Dai, Maoxiang Yi, Dawen Xu, Zhengfeng Huang

Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

2011

Decreasing SoC Test Power Dissipation and Test Data Volume Based on Pattern Recombination.

Chunlei Mei, Maoxiang Yi, Zhifei Shen

Proceedings of the IEEE 10th International Conference on Trust, 2011

2010

A Novel x -ploiting Strategy for Improving Performance of Test Data Compression.

Maoxiang Yi, Huaguo Liang, Lei Zhang, Wenfa Zhan

IEEE Trans. Very Large Scale Integr. Syst., 2010

2009

Optimal LFSR-Coding Test Data Compression Based on Test Cube Dividing.

Maoxiang Yi, Huaguo Liang, Kaihua Zhan, Cuiyun Jiang

Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009

2008

Balancing wrapper chains of SoC core based on best interchange decreasing.

Maoxiang Yi, Huaguo Liang, Zhengfeng Huang

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

2005

A BIST Scheme Based on Selecting State Generation of Folding Counters.

Huaguo Liang, Maoxiang Yi, Xiangsheng Fang, Cuiyun Jiang

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005