Takeshi Sakata

According to our database, Takeshi Sakata authored at least 14 papers between 1985 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2005

A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router.

Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Takayuki Kawahara

IEEE J. Solid State Circuits, 2005

A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup.

Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara

Proceedings of IEEE International Conference on Communications, 2005

1999

A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme.

Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura

IEEE J. Solid State Circuits, 1999

1997

The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory.

Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya

IEEE J. Solid State Circuits, 1997

1995

Low-noise, high-speed data transmission using a ringing-canceling output buffer.

Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki

IEEE J. Solid State Circuits, December, 1995

An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture.

Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda

IEEE J. Solid State Circuits, November, 1995

1994

Two-dimensional power-line selection scheme for low subthreshold-current multi-gigabit DRAM's.

Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki

IEEE J. Solid State Circuits, August, 1994

Subthreshold-current reduction circuits for multi-gigabit DRAM's.

Takeshi Sakata, Kiyoo Itoh, Masashi Horiguchi, Masakazu Aoki

IEEE J. Solid State Circuits, July, 1994

1993

Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's.

Masashi Horiguchi, Takeshi Sakata, Kiyoo Itoh

IEEE J. Solid State Circuits, November, 1993

A high-speed, small-area, threshold-voltage-mismatch compensation sense amplifier for gigabit-scale DRAM arrays.

Takayuki Kawahara, Takeshi Sakata, Kiyoo Itoh, Yoshiki Kawajiri, Takesada Akiba, Goro Kitsukawa, Masakazu Aoki

IEEE J. Solid State Circuits, July, 1993

A single 1.5-V digital chip for a 10⁶ synapse neural network.

Takao Watanabe, Katsutaka Kimura, Masakazu Aoki, Takeshi Sakata, Kiyoo Ito

IEEE Trans. Neural Networks, 1993

1991

A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture.

Katsutaka Kimura, Takeshi Sakata, Kiyoo Itoh, Toru Kaga, Takashi Nishida, Yoshifumi Kawamoto

IEEE J. Solid State Circuits, November, 1991

1990

Studies on the structure and stabilizing factor of the CUUCGG hairpin RNA using chemically synthesized oligonucleotides.

Takeshi Sakata, Hidekazu Hiroaki, Yasushi Oda, Toshiki Tanaka, Morio Ikehara, Seiichi Uesugi

Nucleic Acids Res., 1990

1985

A circuit comparison system for bipolar linear LSI.

Takeshi Sakata, Aritoyo Kishimoto

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985