Taras Iakymchuk

According to our database, Taras Iakymchuk authored at least 14 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks.

Leandro D. Medus, Taras Iakymchuk, José Vicente Francés-Víllora, Manuel Bataller-Mompeán, Alfredo Rosado Muñoz

IEEE Access, 2019

2017

On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems.

Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado, Luis A. Plana, Steve Temple, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco

IEEE Trans. Biomed. Circuits Syst., 2017

An Event-based Fast Movement Detection Algorithm for a Positioning Robot Using POWERLINK Communication.

Juan Barrios-Aviles, Taras Iakymchuk, Jorge Samaniego, Alfredo Rosado Muñoz

CoRR, 2017

Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.

Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Stephen B. Furber, Bernabé Linares-Barranco

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.

Amirreza Yousefzadeh, Miroslaw Jablonski, Taras Iakymchuk, Alejandro Linares-Barranco, Alfredo Rosado Muñoz, Luis A. Plana, Teresa Serrano-Gotarredona, Steve B. Furber, Bernabé Linares-Barranco

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Versatile Direct and Transpose Matrix Multiplication with Chained Operations: An Optimized Architecture Using Circulant Matrices.

Taras Iakymchuk, Alfredo Rosado Muñoz, Manuel Bataller-Mompeán, José Vicente Francés-Víllora, Emmanuel Ovie Osimiry

IEEE Trans. Computers, 2016

Novel Resistance Measurement Method: Analysis of Accuracy and Thermal Dependence with Applications in Fiber Materials.

Silvia Casans Berga, Alfredo Rosado Muñoz, Taras Iakymchuk

Sensors, 2016

Event-based encoding from digital magnetic compass and ultrasonic distance sensor for navigation in mobile systems.

Juan Barrios-Aviles, Taras Iakymchuk, Alfredo Rosado Muñoz, José V. Francés-Víllora, Manuel Bataller-Mompeán, Juan Guerrero-Martínez

Proceedings of the 14th IEEE International Conference on Industrial Informatics, 2016

2015

Simplified spiking neural network architecture and STDP learning algorithm applied to image classification.

Taras Iakymchuk, Alfredo Rosado Muñoz, Juan Guerrero-Martínez, Manuel Bataller-Mompeán, José V. Francés-Víllora

EURASIP J. Image Video Process., 2015

2014

An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links.

Taras Iakymchuk, Alfredo Rosado, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Gabriel Jiménez-Moreno

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2012

Fast spiking neural network architecture for low-cost FPGA devices.

Taras Iakymchuk, Alfredo Rosado, José V. Francés, Manuel Bataller

Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Hardware-efficient matrix inversion algorithm for complex adaptive systems.

Alfredo Rosado, Taras Iakymchuk, Manuel Bataller, Marek Wegrzyn

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Implementation of a new adaptive algorithm using fuzzy cost function and robust to impulsive noise.

Taras Iakymchuk, Alfredo Rosado, Emilio Soria-Olivas, Manuel Bataller

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011

Temperature-based covert channel in FPGA systems.

Taras Iakymchuk, Maciej Nikodem, Krzysztof Kepa

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011