Amirreza Yousefzadeh
Orcid: 0000-0002-2967-5090
According to our database1,
Amirreza Yousefzadeh
authored at least 22 papers
between 2015 and 2023.
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Bibliography
2023
NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking.
CoRR, 2023
Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Empirical study on the efficiency of Spiking Neural Networks with axonal delays, and algorithm-hardware benchmarking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
Delta Activation Layer exploits temporal sparsity for efficient embedded video processing.
Proceedings of the International Joint Conference on Neural Networks, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Training for temporal sparsity in deep neural networks, application in video processing.
CoRR, 2021
2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
NeuronFlow: A Hybrid Neuromorphic - Dataflow Processor Architecture for AI Workloads.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
SpArNet: Sparse Asynchronous Neural Network execution for energy efficient inference.
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Conversion of Synchronous Artificial Neural Network to Asynchronous Spiking Neural Network using sigma-delta quantization.
Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019
2018
Active Perception With Dynamic Vision Sensors. Minimum Saccades With Optimum Recognition.
IEEE Trans. Biomed. Circuits Syst., 2018
Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Hybrid Neural Network, An Efficient Low-Power Digital Hardware Implementation of Event-based Artificial Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs for Scalable Neuromorphic Systems.
IEEE Trans. Biomed. Circuits Syst., 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Live demonstration: Hardware implementation of convolutional STDP for on-line visual feature learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
Fast Predictive Handshaking in Synchronous FPGAs for Fully Asynchronous Multisymbol Chip Links: Application to SpiNNaker 2-of-7 Links.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
2015
Fast Pipeline 128×128 pixel spiking convolution core for event-driven vision processing in FPGAs.
Proceedings of the International Conference on Event-based Control, 2015