Tetsuo Izawa

According to our database, Tetsuo Izawa authored at least 2 papers between 1998 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.

Yisuo Li, Ken'ichi Kanazawa, Tetsuo Izawa, Koji Sakui, Georg Strof, Oskar Baumgartner, Gerhard Rzepa, Markus Karner, Zlatan Stanojevic, Nozomu Harada, Fujio Masuoka

Proceedings of the IEEE International Memory Workshop, 2021

1998

Low-power SRAM design using half-swing pulse-mode techniques.

Kenneth W. Mai, Toshihiko Mori, Bharadwaj S. Amrutur, Ron Ho, Bennett Wilburn, Mark A. Horowitz, Isao Fukushi, Tetsuo Izawa, Shin Mitara

IEEE J. Solid State Circuits, 1998