Markus Karner

According to our database, Markus Karner authored at least 12 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A Study of the Variability and Design Considerations of Ferroelectric VNAND Memories With Polycrystalline Films Using An Experimentally Validated TCAD Model.

M. Thesberg, Franz Schanovsky, Zlatan Stanojevic, Oskar Baumgartner, Markus Karner

Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022

nnU-Net Pre- and Postprocessing Strategies for UW-OCTA Segmentation Tasks in Diabetic Retinopathy Analysis.

Felix Krause, Dominik Heindl, Hana Jebril, Markus Karner, Markus Unterdechler

Proceedings of the Mitosis Domain Generalization and Diabetic Retinopathy Analysis, 2022

A Novel Approach to Modeling Insulator Wave-Function Penetration and Interface Roughness Scattering in MOSFETs.

Zlatan Stanojevic, Lee-Chi Hung, Chen-Ming Tsai, Markus Karner

Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

2021

Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies.

Gerhard Rzepa, Markus Karner, Oskar Baumgartner, Georg Strof, Franz Schanovsky, Ferdinand Mitterbauer, Christian Kernstock, Hui-Wen Karner, Pieter Weckx, Geert Hellings, Dieter Claes, Zhicheng Wu, Yang Xiang, Thomas Chiarella, Bertrand Parvais, Jérôme Mitard, Jacopo Franco, Ben Kaczer, Dimitri Linten, Zlatan Stanojevic

Proceedings of the IEEE International Reliability Physics Symposium, 2021

A TCAD Compatible SONOS Trapping Layer Model for Accurate Programming Dynamics.

Franz Schanovsky, Devin Verreck, Antonio Arreghini, Gerhard Rzepa, Zlatan Stanojevic, Christian Kernstock, Oskar Baumgartner, Maarten Rosmeulen, Markus Karner

Proceedings of the IEEE International Memory Workshop, 2021

1.5-nm Node Surrounding Gate Transistor (SGT)-SRAM Cell with Staggered Pillar and Self-Aligned Process for Gate, Bottom Contact, and Pillar.

Yisuo Li, Ken'ichi Kanazawa, Tetsuo Izawa, Koji Sakui, Georg Strof, Oskar Baumgartner, Gerhard Rzepa, Markus Karner, Zlatan Stanojevic, Nozomu Harada, Fujio Masuoka

Proceedings of the IEEE International Memory Workshop, 2021

2018

Cell Designer - a Comprehensive TCAD-Based Framework for DTCO of Standard Logic Cells.

Zlatan Stanojevic, Georg Strof, Franz Schanovsky, Klaus Steiner, Oskar Baumgartner, Christian Kernstock, Markus Karner

Proceedings of the 48th European Solid-State Device Research Conference, 2018

2015

Predictive physical simulation of III/V quantum-well MISFETs for logic applications.

Zlatan Stanojevic, Markus Karner, Martin Aichhorn, Ferdinand Mitterbauer, Volker Eyert, Christian Kernstock, Hans Kosina

Proceedings of the 45th European Solid State Device Research Conference, 2015

2010

Interface traps density-of-states as a vital component for hot-carrier degradation modeling.

Stanislav Tyaginov, Ivan A. Starkov, Oliver Triebl, Johann Cervenka, C. Jungemann, Sara Carniello, Jong Mun Park, Hubert Enichlmair, Markus Karner, Ch. Kernstock, Ehrenfried Seebacher, Rainer Minixhofer, Hajdin Ceric, Tibor Grasser

Microelectron. Reliab., 2010

2007

VSP - A gate stack analyzer.

Markus Karner, Andreas Gehring, M. Wagner, Robert Entner, Stefan Holzer, Wolfgang Goes, M. Vasicek, Tibor Grasser, Hans Kosina, Siegfried Selberherr

Microelectron. Reliab., 2007

Comparison of deposition models for a TEOS LPCVD process.

Stefan Holzer, Alireza Sheikholeslami, Markus Karner, Tibor Grasser, Siegfried Selberherr

Microelectron. Reliab., 2007

2005

Efficient Calculation of Quasi-bound States for the Simulation of Direct Tunneling.

Markus Karner, Andreas Gehring, Stefan Holzer, Hans Kosina

Proceedings of the Large-Scale Scientific Computing, 5th International Conference, 2005