Ting-Chien Chiu

According to our database, Ting-Chien Chiu authored at least 3 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips.

Ping-Chun Wu, Win-San Khwa, Jui-Jen Wu, Jian-Wei Su, Chuan-Jia Jhang, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang

IEEE J. Solid State Circuits, January, 2025

2024

A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro.

De-Qi You, Win-San Khwa, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices.

Win-San Khwa, Ping-Chun Wu, Jui-Jen Wu, Jian-Wei Su, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024