Jun-Ming Hsu

According to our database, Jun-Ming Hsu authored at least 6 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A Microscaling Multi-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Device.

Jen-Chun Tien, Ping-Chun Wu, Win-San Khwa, Ashwin Sanjay Lele, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang

IEEE J. Solid State Circuits, January, 2026

2025

An Integer-Floating-Point Dual-Mode Gain-Cell Computing-in-Memory Macro for Advanced AI Edge Chips.

Ping-Chun Wu, Win-San Khwa, Jui-Jen Wu, Jian-Wei Su, Chuan-Jia Jhang, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang

IEEE J. Solid State Circuits, January, 2025

14.2 A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro Edge-AI Devices.

Win-San Khwa, Ping-Chun Wu, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Ashwin Sanjay Lele, Jui-Jen Wu, Jen-Chun Tien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

Development of Six-step Voltage Control for IPMSM via Two-degree-of-freedom Torque Control.

Yu-Tse Hsu, Shih-Gang Chen, Jun-Ming Hsu, Ming-Shi Huang

Proceedings of the IEEE Industry Applications Society Annual Meeting, 2025

2024

A 22 nm 10.03-237.99 TOPS/W Time-Digital-Hybrid SRAM Compute-in-Memory AI Accelerator for GNN Edge Device Applications.

Chuan-Jia Jhang, Win-San Khwa, Ping-Chun Wu, Ashwin Sanjay Lele, Ping-Sheng Wu, Chao-En Ke, Ting-Chien Chiu, Yu-Cheng Hung, Wei-Ting Hsu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Jui-Jen Wu, Meng-Fan Chang

IEEE Trans. Circuits Syst. Artif. Intell., September, 2024

34.2 A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices.

Win-San Khwa, Ping-Chun Wu, Jui-Jen Wu, Jian-Wei Su, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu, Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024