Jun Sawada

According to our database1, Jun Sawada authored at least 23 papers between 1997 and 2024.

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Bibliography

2024

2023

2019
TrueNorth: Accelerating From Zero to 64 Million Neurons in 10 Years.
Computer, 2019

The Ambiguity of Tense in the Japanese Mirative Sentence with Nante/Towa.
Proceedings of the New Frontiers in Artificial Intelligence, 2019

2016

2015
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

2013
Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores.
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013

SyNAPSE: Jun Sawada.
Proceedings of the 13th International Conference on Application of Concurrency to System Design, 2013

2011
Hybrid verification of a hardware modular reduction engine.
Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

2010
Automatic verification of estimate functions with polynomials of bounded functions.
Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

2009
Scalable conditional equivalence checking: An automated invariant-generation based approach.
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

2006
Limited switch dynamic logic circuits for high-speed low-power circuit design.
IBM J. Res. Dev., 2006

ACL2SIX: A Hint used to Integrate a Theorem Prover and an Automated Verification Tool.
Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

Combining ACL2 and an automated verification tool to verify a multiplier.
Proceedings of the Sixth International Workshop on the ACL2 Theorem Prover and its Applications, 2006

2002
Verification of FM9801: An Out-of-Order Microprocessor Model with Speculative Execution, Exceptions, and Program-Modifying Capability.
Formal Methods Syst. Des., 2002

Mechanical Verification of a Square Root Algorithm Using Taylor's Theorem.
Proceedings of the Formal Methods in Computer-Aided Design, 4th International Conference, 2002

2001
Derivation of a rotator circuit with homogeneous interconnect.
Inf. Process. Lett., 2001

2000
Hardware Modeling Using Function Encapsulation.
Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000

1999
Verifying the FM9801 microarchitecture.
IEEE Micro, 1999

Results of the Verification of a Complex Pipelined Machine Model.
Proceedings of the Correct Hardware Design and Verification Methods, 1999

1998
Processor Verification with Precise Exeptions and Speculative Execution.
Proceedings of the Computer Aided Verification, 10th International Conference, 1998

1997
Trace Table Based Approach for Pipeline Microprocessor Verification.
Proceedings of the Computer Aided Verification, 9th International Conference, 1997


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