Vladimir Castro Alves

According to our database1, Vladimir Castro Alves authored at least 38 papers between 1991 and 2022.

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Bibliography

2022
Leveraging Computational Storage for Power-Efficient Distributed Data Analytics.
ACM Trans. Embed. Comput. Syst., November, 2022

In-storage Processing of I/O Intensive Applications on Computational Storage Drives.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

2020
Cost-effective, Energy-efficient, and Scalable Storage Computing for Large-scale AI Applications.
ACM Trans. Storage, 2020

STANNIS: Low-Power Acceleration of Deep Neural Network Training Using Computational Storage.
CoRR, 2020

HyperTune: Dynamic Hyperparameter Tuning for Efficient Distribution of DNN Training Over Heterogeneous Systems.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Stannis: Low-Power Acceleration of DNN Training Using Computational Storage Devices.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Computational storage: an efficient and scalable platform for big data and HPC applications.
J. Big Data, 2019

Catalina: In-Storage Processing Acceleration for Scalable Big Data Analytics.
Proceedings of the 27th Euromicro International Conference on Parallel, 2019

A Feasible FPGA Weightless Neural Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Accelerating HPC Applications Using Computational Storage Devices.
Proceedings of the 21st IEEE International Conference on High Performance Computing and Communications; 17th IEEE International Conference on Smart City; 5th IEEE International Conference on Data Science and Systems, 2019

2018
CompStor: An In-storage Computation Platform for Scalable Distributed Processing.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

MPP 2018 Keynote.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

2009
Synchronous-to-Asynchronous Conversion of Cryptographic Circuits.
J. Circuits Syst. Comput., 2009

2002
Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

System on a Chip for Petroleum Pipeline Inspection.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

A Methodology for Dynamic Power Consumption Estimation Using VHDL Descriptions.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

State Model Approach for Analog Fault Modeling.
Proceedings of the 3rd Latin American Test Workshop, 2002

Designing for Test Butterworth and Chebyshev Low-Pass Filters of Any Order.
Proceedings of the 3rd Latin American Test Workshop, 2002

2001
Fault Models and Test Generation for OpAmp Circuits - The FFM.
J. Electron. Test., 2001

Filter Sensitivity Analysis Using the TRAM.
Proceedings of the 2nd Latin American Test Workshop, 2001

Designing Testable Networks for Transfer Function Realization.
Proceedings of the 2nd Latin American Test Workshop, 2001

2000
Design and Implementation of the MorphoSys Reconfigurable Computing Processor.
J. VLSI Signal Process., 2000

Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Implementation of Cryptographic Applications on the Reconfigurable FPGA Coprocessor microEnable.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Improved IDEA.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

Fault Models and Compact Test Vectors for MOS OpAmp circuits.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000

The Use of Macromodels on Op-Amp Circuits Fault Modeling.
Proceedings of the 1st Latin American Test Workshop, 2000

Mixed-Signal Test Bus IEEE 1149.4 Compatible BIST Scheme for Classical 2nd Order Filter Approximations using the Transient Response Analysis Method.
Proceedings of the 1st Latin American Test Workshop, 2000

Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Synchronous to Asynchronous Conversion - A Case Study: the Blowfish Algorithm Implementation.
Proceedings of the VLSI: Systems on a Chip, 1999

An FPGA-Based Fan Beam Image Reconstruction Module.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

The MorphoSys Dynamically Reconfigurable System-on-Chip.
Proceedings of the 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), 1999

1998
Implementation of RNS Addition and RNS Multiplication into FPGAs.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

A BIST Scheme for Asynchronous Logic.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1996
A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
Testing complex couplings in multiport memories.
IEEE Trans. Very Large Scale Integr. Syst., 1995

1994
Trade-offs in scan path and BIST implementations for RAMs.
J. Electron. Test., 1994

1991
Built-In Self-Test for Multi-Port RAMs.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991


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