Walter E. Calienes Bartra

Orcid: 0000-0002-3503-0168

According to our database1, Walter E. Calienes Bartra authored at least 9 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2023
A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

2017
Evaluation of heavy-ion impact in bulk and FDSOI devices under ZTC condition.
Microelectron. Reliab., 2017

Process and temperature impact on single-event transients in 28nm FDSOI CMOS.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2016
FDSOI and Bulk CMOS SRAM Cell Resilience to Radiation Effects.
Microelectron. Reliab., 2016

2015
Modeling the impact of heavy ion on FDSOI NanoCMOS.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Bulk and FDSOI Sub-micron CMOS transistors resilience to single-event transients.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
Bulk and FDSOI SRAM resiliency to radiation effects.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A set of Virtual Instruments to simulate radiation effects in CMOS circuits.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2014

2012
Simulation of SET faults in a voltage controlled oscillator.
Proceedings of the 13th Latin American Test Workshop, 2012


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