Leonardo Heitich Brendler

Orcid: 0000-0002-8055-9597

Affiliations:
  • Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil


According to our database1, Leonardo Heitich Brendler authored at least 15 papers between 2018 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
A Proof-of-Concept of a Multiple-Cell Upsets Detection Method for SRAMs in Space Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

A MCU-robust Interleaved Data/Detection SRAM for Space Environments.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

Impact on Radiation Robustness of Gate Mapping in FinFET Circuits under Work-function Fluctuation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Tool for Automatic Radiation-Hardened SRAM Layout Generation.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2021
Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

2020
Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Circuit Level Design Methods to Mitigate Soft Errors.
Proceedings of the IEEE Latin-American Test Symposium, 2020

Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters.
Proceedings of the IEEE Latin-American Test Symposium, 2020

2019
Impact of Process Variability and Single Event Transient on FinFET Technology.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Evaluation of SET under Process Variability on FinFET Multi-level Design.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Process Variability Impact on the SET Response of FinFET Multi-level Design.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019

2018
Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Exploring Multi-level Design to Mitigate Variability and Radiation Effects on 7nm FinFET Logic Cells.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018


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