Alexandra L. Zimpeck

Alexander Fish

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2024

2023

Robustness Analysis of 3-2 Adder Compressor Designed in 7-nm FinFET Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, March, 2023

An Approach to Remote Update Embedded Systems in the Internet of Things.

[BibT_eX]

[DOI]

J. Internet Serv. Appl., January, 2023

A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures.

[BibT_eX]

[DOI]

Cleiton Magano Marques

Frédéric Wrobel

Walter E. Calienes Bartra

Paulo F. Butzen

Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Impact on Radiation Robustness of Gate Mapping in FinFET Circuits under Work-function Fluctuation.

[BibT_eX]

[DOI]

Bernardo Borges Sandoval

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Fast and Low-Error Prediction of Logic Gate Cell Characterization.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022

Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology.

[BibT_eX]

[DOI]

Fábio G. R. G. da Silva

Rafael N. M. Oliveira

Integr., 2022

2021

Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study.

[BibT_eX]

[DOI]

Bernardo Borges Sandoval

Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

Current Behavior on Process Variability Aware FinFET Inverter Designs.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Sensitivity of FinFET Adders to PVT Variations and Sleep Transistor as a Mitigation Strategy.

[BibT_eX]

[DOI]

Gerson D. Andrade

Eduardo A. C. da Costa

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020

Multi-Level Design Influences on Robustness Evaluation of 7nm FinFET Technology.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Circuit Level Design Methods to Mitigate Soft Errors.

[BibT_eX]

[DOI]

Proceedings of the IEEE Latin-American Test Symposium, 2020

Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters.

[BibT_eX]

[DOI]

Proceedings of the IEEE Latin-American Test Symposium, 2020

Pros and Cons of ST and SIG FinFET Inverters for Low Power Designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Robust FinFET Schmitt Trigger Designs for Low Power Applications.

[BibT_eX]

[DOI]

Alexandra Lackmann Zimpeck

Proceedings of the VLSI-SoC: New Technology Enabler, 2019

Robustness and Minimum Energy-Oriented FinFET Design.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Impact of Process Variability and Single Event Transient on FinFET Technology.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Evaluation of SET under Process Variability on FinFET Multi-level Design.

[BibT_eX]

[DOI]

Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Process Variability Impact on the SET Response of FinFET Multi-level Design.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: New Technology Enabler, 2019

Exploring Schmitt Trigger Circuits for Process Variability Mitigation.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018

Impact of different transistor arrangements on gate variability.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

Evaluation of variability using Schmitt trigger on full adders layout.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Pros and Cons of Schmitt Trigger Inverters to Mitigate PVT Variability on Full Adders.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Exploring Multi-level Design to Mitigate Variability and Radiation Effects on 7nm FinFET Logic Cells.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

Robustness of Sub-22nm multigate devices against physical variability.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Impact of schmitt trigger inverters on process variability robustness of 1-Bit full adders.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

Temperature dependence and ZTC bias point evaluation of sub 20nm bulk multigate devices.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016

Permanent and single event transient faults reliability evaluation EDA tool.

[BibT_eX]

[DOI]

Y. Q. de Aguiar

Microelectron. Reliab., 2016

FinFET cells with different transistor sizing techniques against PVT variations.

[BibT_eX]

[DOI]

Gracieli Posser

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Impact of variability effects on FinFET transistors and combinational cells.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Geometric variability impact on 7nm Trigate combinational cells.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

Impact of PVT variability on 20 nm FinFET standard cells.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2015

Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-Flops.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Process variability in FinFET standard cells with different transistor sizing techniques.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2014

Evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devices.

[BibT_eX]

[DOI]

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Impact of gate workfunction fluctuation on FinFET standard cells.

[BibT_eX]

[DOI]