Wei-Han Yu
Orcid: 0000-0002-9079-5227
According to our database1,
Wei-Han Yu
authored at least 44 papers
between 2012 and 2025.
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Bibliography
2025
A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW<sup>2</sup> Pipeline and Adaptive-Resolution Quantization.
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2025
An 800-MHz 8.17-TOPS/W 0.63-TOPS/mm<sup>2</sup> Memory-Utilization-Aware CNN Accelerator Featuring a Memory Stationary Dataflow.
IEEE J. Solid State Circuits, August, 2025
A 28-nm MFCC-Free Keyword Switchable Keyword Spotting (KWS) System With Transferred Training Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2025
GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2025
A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM.
IEEE J. Solid State Circuits, March, 2025
A 90.7-nW Vibration-Based Condition Monitoring Chip Featuring a Digital Compute-in-Memory- Based DNN Accelerator Using an Ultra-Low-Power 13T-SRAM Cell.
IEEE J. Solid State Circuits, January, 2025
On the Usage of Genetic Algorithms, Reinforcement Learning and Bayesian Optimisation for RF IC Design Automation.
Proceedings of the 21st International Conference on Synthesis, 2025
A 94.8nW Battery-Free Intelligent Silicon Platform Enabling Distributed, Adaptive, and Event-Driven Multimodal Sensing at the Edge.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
Proceedings of the 6th International Conference on Computing, 2025
2024
A 512-nW 0.003-mm² Forward-Forward Closed Box Trainer for an Analog Voice Activity Detector in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024
An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2024
CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024
A 28-nm 18.7 TOPS/mm² 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh.
IEEE J. Solid State Circuits, November, 2024
IEEE J. Solid State Circuits, November, 2024
FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm<sup>2</sup> Analog Compute-in-Memory Macro.
IEEE J. Solid State Circuits, September, 2024
A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024
A 1024-Channel 268-nW/Pixel 36×36 μm<sup>2</sup>/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces.
IEEE J. Solid State Circuits, April, 2024
A 0.05-mm<sup>2</sup> 2.91-nJ/Decision Keyword-Spotting (KWS) Chip Featuring an Always-Retention 5T-SRAM in 28-nm CMOS.
IEEE J. Solid State Circuits, February, 2024
A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2024
2023
A 47-nW Voice Activity Detector (VAD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-Volatile CAP-ROM.
IEEE J. Solid State Circuits, November, 2023
An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2023
A 1024-Channel 268 nW/pixel 36x36 μm<sup>2</sup>/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A ULP Long-Range Active-RF Tag with Automatic Antenna-Interface Calibration Achieving 20.5% TX Efficiency at -22dBm EIRP, and -60.4dBm Sensitivity at 17.8nW RX Power.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature Extractor and an RNN Classifier.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 108-nW 0.8-mm<sup>2</sup> Analog Voice Activity Detector Featuring a Time-Domain CNN With Sparsity-Aware Computation and Sparsified Quantization in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022
A 108nW 0.8mm<sup>2</sup> Analog Voice Activity Detector (VAD) Featuring a Time-Domain CNN as a Programmable Feature Extractor and a Sparsity-Aware Computational Scheme in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2019
A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019
2018
A 0.7-2.5 GHz, 61% EIRP System Efficiency, Four-Element MIMO TX System Exploiting Integrated Power-Relaxed Power Amplifiers and an Analog Spatial De-Interleaver.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A Coin-Battery-Powered LDO-Free 2.4-GHz Bluetooth Low-Energy Transmitter With 34.7% Peak System Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 0.18-V 382-µW Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS.
IEEE J. Solid State Circuits, 2018
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
A High-Voltage-Enabled Class-D Polar PA Using Interactive AM-AM Modulation, Dynamic Matching, and Power-Gating for Average PAE Enhancement.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6% (14.5%) System Efficiency at 6-dBm (0-dBm) P<sub>out</sub>.
IEEE J. Solid State Circuits, 2017
24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2015
A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
2013
A Nonrecursive Digital Calibration Technique for Joint Elimination of Transmitter and Receiver I/Q Imbalances With Minimized Add-On Hardware.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
2012
A dynamic-range-improved 2.4GHz WLAN class-E PA combining PWPM and cascode modulation.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012