Weier Wan

According to our database, Weier Wan authored at least 8 papers between 2016 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

When Models Know When They Do Not Know: Calibration, Cascading, and Cleaning.

Chenjie Hao, Weyl Lu, Yuko Ishiwaka, Zengyi Li, Weier Wan, Yubei Chen

CoRR, January, 2026

2025

PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro With In Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout.

Zhiyu Chen, Ziyuan Wen, Weier Wan, Akhil Reddy Pakala, Yiwei Zou, Wei-Chen Wei, Zengyi Li, Yubei Chen, Kaiyuan Yang

IEEE J. Solid State Circuits, January, 2025

2022

A compute-in-memory chip based on resistive random-access memory.

Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs

Nat., 2022

2021

Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory.

Weier Wan, Rajkumar Kubendran, Clemens J. S. Schaefer, Sukru Burc Eryilmaz, Wenqiang Zhang, Dabin Wu, Stephen R. Deiss, Priyanka Raina, He Qian, Bin Gao, Siddharth Joshi, Huaqiang Wu, H.-S. Philip Wong, Gert Cauwenberghs

CoRR, 2021

2020

33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models.

Weier Wan, Rajkumar Kubendran, Sukru Burc Eryilmaz, Wenqiang Zhang, Yan Liao, Dabin Wu, Stephen R. Deiss, Bin Gao, Priyanka Raina, Siddharth Joshi, Huaqiang Wu, Gert Cauwenberghs, H.-S. Philip Wong

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver.

Rajkumar Kubendran, Weier Wan, Siddharth Joshi, H.-S. Philip Wong, Gert Cauwenberghs

Proceedings of the International Conference on Neuromorphic Systems, 2020

2018

Coming Up N3XT, After 2D Scaling of Si CMOS.

William Hwang, Weier Wan, Subhasish Mitra, H.-S. Philip Wong

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016

Neuromorphic architectures with electronic synapses.

Sukru Burc Eryilmaz, Siddharth Joshi, Emre Neftci, Weier Wan, Gert Cauwenberghs, H.-S. Philip Wong

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016