Wolfgang Hokenmaier

According to our database, Wolfgang Hokenmaier authored at least 4 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Co-design of a novel CMOS highly parallel, low-power, multi-chip neural network accelerator.

Wolfgang Hokenmaier, Ryan Jurasek, Elijah F. W. Bowen, R. Granger, D. Odom

CoRR, 2024

2020

Verification and Testing Considerations of an In-Memory AI Chip.

Marcia Golmohamadi, Ryan Jurasek, Wolfgang Hokenmaier, Donald Labrecque, Ruoyu Zhi, Bret Dale, Nibir Islam, Dave Kinney, Angela Johnson

Proceedings of the 29th IEEE North Atlantic Test Workshop, 2020

2018

An analysis of an inexpensive memory test solution.

Ryan Pennucci, Ryan Jurasek, Wolfgang Hokenmaier, Lester Patrick, Jacob Bucci, Donald Labrecque, David Kinney

Proceedings of the 27th IEEE North Atlantic Test Workshop, 2018

2005

A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems.

Joseph T. Kennedy, Randy Mooney, Robert Ellis, James E. Jaussi, Shekhar Borkar, Jung-Hwan Choi, Jae-Kwan Kim, Chan-Kyong Kim, Woo-Seop Kim, Chang-Hyun Kim, Soo-In Cho, Steffen Loeffler, Jochen Hoffmann, Wolfgang Hokenmaier, Russ Houghton, Thomas Vogelsang

IEEE J. Solid State Circuits, 2005