Thomas Vogelsang

Orcid: 0000-0001-5513-5197

According to our database1, Thomas Vogelsang authored at least 11 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Unraveling codes: fast, robust, beyond-bound error correction for DRAM.
CoRR, 2024

2021
DRAM Refresh with Master Wordline Granularity Control of Refresh Intervals: Position Paper.
Proceedings of the MEMSYS 2021: The International Symposium on Memory Systems, Washington, USA, September 27, 2021

2017
Do superconducting processors really need cryogenic memories?: the case for cold DRAM.
Proceedings of the International Symposium on Memory Systems, 2017

Reducing electrical power dissipation in computational imaging systems through special-purpose optics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Optimization of CMOS Image Sensor Utilizing Variable Temporal Multi-Sampling Partial Transfer Technique to Achieve Full-frame High Dynamic Range with Superior Low Light and Stop Motion Capability.
Proceedings of the Image Sensors and Imaging Systems 2017, 2017

2016
Reduction of CMOS Image Sensor Read Noise to Enable Photon Counting.
Sensors, 2016

Lensless Smart Sensors: Optical and thermal sensing for the Internet of Things.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2014
Hardware validated unified model of multibit temporally and spatially oversampled image sensors with conditional reset.
J. Electronic Imaging, 2014

2013
Multichannel sampling of low light level scenes with unknown shifts.
Proceedings of the IEEE International Conference on Image Processing, 2013

2010
Understanding the Energy Consumption of Dynamic Random Access Memories.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

2005
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems.
IEEE J. Solid State Circuits, 2005


  Loading...