Woosong Jung
Orcid: 0000-0002-7470-1630
According to our database1,
Woosong Jung
authored at least 12 papers
between 2020 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2023
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
A 48 Gb/s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS.
IEEE J. Solid State Circuits, May, 2023
A 14-28 Gb/s Reference-less Baud-rate CDR with Integrator-based Stochastic Phase and Frequency Detector.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation.
IEEE J. Solid State Circuits, 2022
Design Techniques for 48-Gb/s 2.4-pJ/b PAM-4 Baud-Rate CDR With Stochastic Phase Detector.
IEEE J. Solid State Circuits, 2022
A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 48Gb/s 2.4pJ/b PAM-4 Baud-Rate Digital CDR with Stochastic Phase Detection Technique in 40nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40: 1 Serializer for DisplayPort Interface.
Proceedings of the International SoC Design Conference, 2020